/*
 * Copyright (c) 2021-2024 HPMicro
 *
 * SPDX-License-Identifier: BSD-3-Clause
 *
 */


#ifndef HPM_MTG_H
#define HPM_MTG_H

typedef struct {
    struct {
        __RW uint32_t CONTROL;                 /* 0x0: tra_control */
        __RW uint32_t SHIFT;                   /* 0x4: tra_shift */
        __RW uint32_t LINK;                    /* 0x8: tra_link */
        __R  uint8_t  RESERVED0[20];           /* 0xC - 0x1F: Reserved */
        struct {
            __RW uint32_t CONTROL;             /* 0x20: tra_cmd_control */
            __RW uint32_t REV_PRESET;          /* 0x24: tra_cmd_rev_preset */
            __RW uint32_t POS_PRESET;          /* 0x28: tra_cmd_pos_preset */
            __RW uint32_t VEL_PRESET;          /* 0x2C: tra_cmd_vel_preset */
            __RW uint32_t ACC_PRESET;          /* 0x30: tra_cmd_acc_preset */
            __RW uint32_t JER_PRESET;          /* 0x34: tra_cmd_jer_preset */
            __R  uint32_t TIMESTAMP;           /* 0x38: tra_cmd_timestamp */
            __R  uint8_t  RESERVED0[4];        /* 0x3C - 0x3F: Reserved */
        } CMD[4];
        __R  uint32_t LOCK_REV;                /* 0xA0: tra_lock_rev */
        __R  uint32_t LOCK_POS;                /* 0xA4: tra_lock_pos */
        __R  uint32_t LOCK_VEL;                /* 0xA8: tra_lock_vel */
        __R  uint32_t LOCK_ACC;                /* 0xAC: tra_lock_acc */
        __R  uint32_t LOCK_TIME;               /* 0xB0: tra_lock_time */
        __R  uint8_t  RESERVED1[12];           /* 0xB4 - 0xBF: Reserved */
        __RW uint32_t STEP_LIMIT_CTRL;         /* 0xC0: tra_step_limit_ctrl */
        __RW uint32_t VEL_STEP_MAX;            /* 0xC4: tra_vel_step_max */
        __RW uint32_t VEL_STEP_MIN;            /* 0xC8: tra_vel_step_min */
        __RW uint32_t POS_STEP_MAX;            /* 0xCC: tra_pos_step_max */
        __RW uint32_t POS_STEP_MIN;            /* 0xD0: tra_pos_step_min */
        __RW uint32_t VEL_LIMIT_P;             /* 0xD4: tra_vel_limit_p */
        __RW uint32_t VEL_LIMIT_N;             /* 0xD8: tra_vel_limit_n */
        __R  uint8_t  RESERVED2[3876];         /* 0xDC - 0xFFF: Reserved */
    } TRA[2];
    struct {
        __RW uint32_t CONTROL;                 /* 0x2000: event_control */
        __RW uint32_t PRESET_0;                /* 0x2004: event_preset_0 */
        __RW uint32_t PRESET_1;                /* 0x2008: event_preset_1 */
        __RW uint32_t PRESET_2;                /* 0x200C: event_preset_2 */
        __RW uint32_t PRESET_3;                /* 0x2010: event_preset_3 */
        __R  uint32_t TIMESTAMP;               /* 0x2014: event_timestamp */
        __R  uint8_t  RESERVED0[8];            /* 0x2018 - 0x201F: Reserved */
    } EVENT[4];
    __RW uint32_t SW_EVENT;                    /* 0x2080: sw_event */
    __W  uint32_t SW_GLB_RESET;                /* 0x2084: sw_glb_reset */
    __R  uint8_t  RESERVED0[3960];             /* 0x2088 - 0x2FFF: Reserved */
    __RW uint32_t FILTER_CONTROL;              /* 0x3000: filter_control */
    __R  uint8_t  RESERVED1[12];               /* 0x3004 - 0x300F: Reserved */
    __RW uint32_t FILTER_REV_VALUE;            /* 0x3010: filter_rev_value */
    __RW uint32_t FILTER_POS_VALUE;            /* 0x3014: filter_pos_value */
    __RW uint32_t FILTER_VEL_VALUE;            /* 0x3018: filter_vel_value */
    __RW uint32_t FILTER_ACC_VALUE;            /* 0x301C: filter_acc_value */
    __RW uint32_t FILTER_MOT_SEL;              /* 0x3020: filter_mot_sel */
    __RW uint32_t FILTER_STAGE_SEL;            /* 0x3024: filter_stage_sel */
    __RW uint32_t FILTER_TIME_CONSTANT_TP;     /* 0x3028: filter_time_constant_tp */
    __RW uint32_t FILTER_TIME_CONSTANT_TZ;     /* 0x302C: filter_time_constant_tz */
    __RW uint32_t FILTER_TIME_CONSTANT_TZ_1;   /* 0x3030: filter_time_constant_tz_1 */
    __RW uint32_t FILTER_ZERO_TZ_SEL;          /* 0x3034: filter_zero_tz_sel */
    __RW uint32_t FILTER_GAIN;                 /* 0x3038: filter_gain */
    __RW uint32_t FILTER_STAGE_SHIFT0;         /* 0x303C: filter_stage_shift0 */
    __RW uint32_t FILTER_STAGE_SHIFT1;         /* 0x3040: filter_stage_shift1 */
    __RW uint32_t FILTER_PARAM_SHIFT;          /* 0x3044: filter_param_shift */
    __RW uint32_t FILTER_TIME_SHIFT;           /* 0x3048: filter_time_shift */
    __RW uint32_t FILTER_FF_SHIFT;             /* 0x304C: filter_ff_shift */
    __RW uint32_t FILTER_TIME1_SW_ADJUST;      /* 0x3050: filter_time1_sw_adjust */
    __RW uint32_t FILTER_TIME0_SW_ADJUST;      /* 0x3054: filter_time0_sw_adjust */
    __R  uint8_t  RESERVED2[8];                /* 0x3058 - 0x305F: Reserved */
    __RW uint32_t FILTER_ERROR_LIMIT_L;        /* 0x3060: filter_error_limit */
    __RW uint32_t FILTER_ERROR_LIMIT_H;        /* 0x3064: filter_error_limit */
    __R  uint8_t  RESERVED3[4];                /* 0x3068 - 0x306B: Reserved */
    __RW uint32_t FILTER_TIMEOUT_CNT;          /* 0x306C: filter_timeout_cnt */
    __R  uint32_t FILTER_REV_LOCK;             /* 0x3070: filter_rev_lock */
    __R  uint32_t FILTER_POS_LOCK;             /* 0x3074: filter_pos_lock */
    __R  uint32_t FILTER_VEL_LOCK;             /* 0x3078: filter_vel_lock */
    __R  uint32_t FILTER_ACC_LOCK;             /* 0x307C: filter_acc_lock */
} MTG_Type;


/* Bitfield definition for register of struct array TRA: CONTROL */
/*
 * CMD_FAIL_IRQ_EN (RW)
 *
 */
#define MTG_TRA_CONTROL_CMD_FAIL_IRQ_EN_MASK (0x20U)
#define MTG_TRA_CONTROL_CMD_FAIL_IRQ_EN_SHIFT (5U)
#define MTG_TRA_CONTROL_CMD_FAIL_IRQ_EN_SET(x) (((uint32_t)(x) << MTG_TRA_CONTROL_CMD_FAIL_IRQ_EN_SHIFT) & MTG_TRA_CONTROL_CMD_FAIL_IRQ_EN_MASK)
#define MTG_TRA_CONTROL_CMD_FAIL_IRQ_EN_GET(x) (((uint32_t)(x) & MTG_TRA_CONTROL_CMD_FAIL_IRQ_EN_MASK) >> MTG_TRA_CONTROL_CMD_FAIL_IRQ_EN_SHIFT)

/*
 * LOCK_IRQ_EN (RW)
 *
 */
#define MTG_TRA_CONTROL_LOCK_IRQ_EN_MASK (0x10U)
#define MTG_TRA_CONTROL_LOCK_IRQ_EN_SHIFT (4U)
#define MTG_TRA_CONTROL_LOCK_IRQ_EN_SET(x) (((uint32_t)(x) << MTG_TRA_CONTROL_LOCK_IRQ_EN_SHIFT) & MTG_TRA_CONTROL_LOCK_IRQ_EN_MASK)
#define MTG_TRA_CONTROL_LOCK_IRQ_EN_GET(x) (((uint32_t)(x) & MTG_TRA_CONTROL_LOCK_IRQ_EN_MASK) >> MTG_TRA_CONTROL_LOCK_IRQ_EN_SHIFT)

/*
 * CMD_FAIL_IRQ (W1C)
 *
 */
#define MTG_TRA_CONTROL_CMD_FAIL_IRQ_MASK (0x8U)
#define MTG_TRA_CONTROL_CMD_FAIL_IRQ_SHIFT (3U)
#define MTG_TRA_CONTROL_CMD_FAIL_IRQ_SET(x) (((uint32_t)(x) << MTG_TRA_CONTROL_CMD_FAIL_IRQ_SHIFT) & MTG_TRA_CONTROL_CMD_FAIL_IRQ_MASK)
#define MTG_TRA_CONTROL_CMD_FAIL_IRQ_GET(x) (((uint32_t)(x) & MTG_TRA_CONTROL_CMD_FAIL_IRQ_MASK) >> MTG_TRA_CONTROL_CMD_FAIL_IRQ_SHIFT)

/*
 * LOCK_IRQ (W1C)
 *
 */
#define MTG_TRA_CONTROL_LOCK_IRQ_MASK (0x4U)
#define MTG_TRA_CONTROL_LOCK_IRQ_SHIFT (2U)
#define MTG_TRA_CONTROL_LOCK_IRQ_SET(x) (((uint32_t)(x) << MTG_TRA_CONTROL_LOCK_IRQ_SHIFT) & MTG_TRA_CONTROL_LOCK_IRQ_MASK)
#define MTG_TRA_CONTROL_LOCK_IRQ_GET(x) (((uint32_t)(x) & MTG_TRA_CONTROL_LOCK_IRQ_MASK) >> MTG_TRA_CONTROL_LOCK_IRQ_SHIFT)

/*
 * SW_LOCK (RW)
 *
 */
#define MTG_TRA_CONTROL_SW_LOCK_MASK (0x2U)
#define MTG_TRA_CONTROL_SW_LOCK_SHIFT (1U)
#define MTG_TRA_CONTROL_SW_LOCK_SET(x) (((uint32_t)(x) << MTG_TRA_CONTROL_SW_LOCK_SHIFT) & MTG_TRA_CONTROL_SW_LOCK_MASK)
#define MTG_TRA_CONTROL_SW_LOCK_GET(x) (((uint32_t)(x) & MTG_TRA_CONTROL_SW_LOCK_MASK) >> MTG_TRA_CONTROL_SW_LOCK_SHIFT)

/*
 * OVALID_CLEAR (RW)
 *
 */
#define MTG_TRA_CONTROL_OVALID_CLEAR_MASK (0x1U)
#define MTG_TRA_CONTROL_OVALID_CLEAR_SHIFT (0U)
#define MTG_TRA_CONTROL_OVALID_CLEAR_SET(x) (((uint32_t)(x) << MTG_TRA_CONTROL_OVALID_CLEAR_SHIFT) & MTG_TRA_CONTROL_OVALID_CLEAR_MASK)
#define MTG_TRA_CONTROL_OVALID_CLEAR_GET(x) (((uint32_t)(x) & MTG_TRA_CONTROL_OVALID_CLEAR_MASK) >> MTG_TRA_CONTROL_OVALID_CLEAR_SHIFT)

/* Bitfield definition for register of struct array TRA: SHIFT */
/*
 * ACC_SHIFT_FAIL_IRQ (W1C)
 *
 */
#define MTG_TRA_SHIFT_ACC_SHIFT_FAIL_IRQ_MASK (0x80000000UL)
#define MTG_TRA_SHIFT_ACC_SHIFT_FAIL_IRQ_SHIFT (31U)
#define MTG_TRA_SHIFT_ACC_SHIFT_FAIL_IRQ_SET(x) (((uint32_t)(x) << MTG_TRA_SHIFT_ACC_SHIFT_FAIL_IRQ_SHIFT) & MTG_TRA_SHIFT_ACC_SHIFT_FAIL_IRQ_MASK)
#define MTG_TRA_SHIFT_ACC_SHIFT_FAIL_IRQ_GET(x) (((uint32_t)(x) & MTG_TRA_SHIFT_ACC_SHIFT_FAIL_IRQ_MASK) >> MTG_TRA_SHIFT_ACC_SHIFT_FAIL_IRQ_SHIFT)

/*
 * VEL_SHIFT_FAIL_IRQ (W1C)
 *
 */
#define MTG_TRA_SHIFT_VEL_SHIFT_FAIL_IRQ_MASK (0x40000000UL)
#define MTG_TRA_SHIFT_VEL_SHIFT_FAIL_IRQ_SHIFT (30U)
#define MTG_TRA_SHIFT_VEL_SHIFT_FAIL_IRQ_SET(x) (((uint32_t)(x) << MTG_TRA_SHIFT_VEL_SHIFT_FAIL_IRQ_SHIFT) & MTG_TRA_SHIFT_VEL_SHIFT_FAIL_IRQ_MASK)
#define MTG_TRA_SHIFT_VEL_SHIFT_FAIL_IRQ_GET(x) (((uint32_t)(x) & MTG_TRA_SHIFT_VEL_SHIFT_FAIL_IRQ_MASK) >> MTG_TRA_SHIFT_VEL_SHIFT_FAIL_IRQ_SHIFT)

/*
 * SHIFT_FAIL_EN (RW)
 *
 */
#define MTG_TRA_SHIFT_SHIFT_FAIL_EN_MASK (0x20000000UL)
#define MTG_TRA_SHIFT_SHIFT_FAIL_EN_SHIFT (29U)
#define MTG_TRA_SHIFT_SHIFT_FAIL_EN_SET(x) (((uint32_t)(x) << MTG_TRA_SHIFT_SHIFT_FAIL_EN_SHIFT) & MTG_TRA_SHIFT_SHIFT_FAIL_EN_MASK)
#define MTG_TRA_SHIFT_SHIFT_FAIL_EN_GET(x) (((uint32_t)(x) & MTG_TRA_SHIFT_SHIFT_FAIL_EN_MASK) >> MTG_TRA_SHIFT_SHIFT_FAIL_EN_SHIFT)

/*
 * JER_SHIFT (RW)
 *
 */
#define MTG_TRA_SHIFT_JER_SHIFT_MASK (0x700U)
#define MTG_TRA_SHIFT_JER_SHIFT_SHIFT (8U)
#define MTG_TRA_SHIFT_JER_SHIFT_SET(x) (((uint32_t)(x) << MTG_TRA_SHIFT_JER_SHIFT_SHIFT) & MTG_TRA_SHIFT_JER_SHIFT_MASK)
#define MTG_TRA_SHIFT_JER_SHIFT_GET(x) (((uint32_t)(x) & MTG_TRA_SHIFT_JER_SHIFT_MASK) >> MTG_TRA_SHIFT_JER_SHIFT_SHIFT)

/*
 * ACC_SHIFT (RW)
 *
 */
#define MTG_TRA_SHIFT_ACC_SHIFT_MASK (0x70U)
#define MTG_TRA_SHIFT_ACC_SHIFT_SHIFT (4U)
#define MTG_TRA_SHIFT_ACC_SHIFT_SET(x) (((uint32_t)(x) << MTG_TRA_SHIFT_ACC_SHIFT_SHIFT) & MTG_TRA_SHIFT_ACC_SHIFT_MASK)
#define MTG_TRA_SHIFT_ACC_SHIFT_GET(x) (((uint32_t)(x) & MTG_TRA_SHIFT_ACC_SHIFT_MASK) >> MTG_TRA_SHIFT_ACC_SHIFT_SHIFT)

/*
 * VEL_SHIFT (RW)
 *
 */
#define MTG_TRA_SHIFT_VEL_SHIFT_MASK (0xFU)
#define MTG_TRA_SHIFT_VEL_SHIFT_SHIFT (0U)
#define MTG_TRA_SHIFT_VEL_SHIFT_SET(x) (((uint32_t)(x) << MTG_TRA_SHIFT_VEL_SHIFT_SHIFT) & MTG_TRA_SHIFT_VEL_SHIFT_MASK)
#define MTG_TRA_SHIFT_VEL_SHIFT_GET(x) (((uint32_t)(x) & MTG_TRA_SHIFT_VEL_SHIFT_MASK) >> MTG_TRA_SHIFT_VEL_SHIFT_SHIFT)

/* Bitfield definition for register of struct array TRA: LINK */
/*
 * LINK_CFG_3 (RW)
 *
 */
#define MTG_TRA_LINK_LINK_CFG_3_MASK (0x7000U)
#define MTG_TRA_LINK_LINK_CFG_3_SHIFT (12U)
#define MTG_TRA_LINK_LINK_CFG_3_SET(x) (((uint32_t)(x) << MTG_TRA_LINK_LINK_CFG_3_SHIFT) & MTG_TRA_LINK_LINK_CFG_3_MASK)
#define MTG_TRA_LINK_LINK_CFG_3_GET(x) (((uint32_t)(x) & MTG_TRA_LINK_LINK_CFG_3_MASK) >> MTG_TRA_LINK_LINK_CFG_3_SHIFT)

/*
 * LINK_CFG_2 (RW)
 *
 */
#define MTG_TRA_LINK_LINK_CFG_2_MASK (0x700U)
#define MTG_TRA_LINK_LINK_CFG_2_SHIFT (8U)
#define MTG_TRA_LINK_LINK_CFG_2_SET(x) (((uint32_t)(x) << MTG_TRA_LINK_LINK_CFG_2_SHIFT) & MTG_TRA_LINK_LINK_CFG_2_MASK)
#define MTG_TRA_LINK_LINK_CFG_2_GET(x) (((uint32_t)(x) & MTG_TRA_LINK_LINK_CFG_2_MASK) >> MTG_TRA_LINK_LINK_CFG_2_SHIFT)

/*
 * LINK_CFG_1 (RW)
 *
 */
#define MTG_TRA_LINK_LINK_CFG_1_MASK (0x70U)
#define MTG_TRA_LINK_LINK_CFG_1_SHIFT (4U)
#define MTG_TRA_LINK_LINK_CFG_1_SET(x) (((uint32_t)(x) << MTG_TRA_LINK_LINK_CFG_1_SHIFT) & MTG_TRA_LINK_LINK_CFG_1_MASK)
#define MTG_TRA_LINK_LINK_CFG_1_GET(x) (((uint32_t)(x) & MTG_TRA_LINK_LINK_CFG_1_MASK) >> MTG_TRA_LINK_LINK_CFG_1_SHIFT)

/*
 * LINK_CFG_0 (RW)
 *
 */
#define MTG_TRA_LINK_LINK_CFG_0_MASK (0x7U)
#define MTG_TRA_LINK_LINK_CFG_0_SHIFT (0U)
#define MTG_TRA_LINK_LINK_CFG_0_SET(x) (((uint32_t)(x) << MTG_TRA_LINK_LINK_CFG_0_SHIFT) & MTG_TRA_LINK_LINK_CFG_0_MASK)
#define MTG_TRA_LINK_LINK_CFG_0_GET(x) (((uint32_t)(x) & MTG_TRA_LINK_LINK_CFG_0_MASK) >> MTG_TRA_LINK_LINK_CFG_0_SHIFT)

/* Bitfield definition for register of struct array TRA: CONTROL */
/*
 * PASS_IRQ (W1C)
 *
 */
#define MTG_TRA_CMD_CONTROL_PASS_IRQ_MASK (0x80000000UL)
#define MTG_TRA_CMD_CONTROL_PASS_IRQ_SHIFT (31U)
#define MTG_TRA_CMD_CONTROL_PASS_IRQ_SET(x) (((uint32_t)(x) << MTG_TRA_CMD_CONTROL_PASS_IRQ_SHIFT) & MTG_TRA_CMD_CONTROL_PASS_IRQ_MASK)
#define MTG_TRA_CMD_CONTROL_PASS_IRQ_GET(x) (((uint32_t)(x) & MTG_TRA_CMD_CONTROL_PASS_IRQ_MASK) >> MTG_TRA_CMD_CONTROL_PASS_IRQ_SHIFT)

/*
 * PASS_IRQ_EN (RW)
 *
 */
#define MTG_TRA_CMD_CONTROL_PASS_IRQ_EN_MASK (0x40000000UL)
#define MTG_TRA_CMD_CONTROL_PASS_IRQ_EN_SHIFT (30U)
#define MTG_TRA_CMD_CONTROL_PASS_IRQ_EN_SET(x) (((uint32_t)(x) << MTG_TRA_CMD_CONTROL_PASS_IRQ_EN_SHIFT) & MTG_TRA_CMD_CONTROL_PASS_IRQ_EN_MASK)
#define MTG_TRA_CMD_CONTROL_PASS_IRQ_EN_GET(x) (((uint32_t)(x) & MTG_TRA_CMD_CONTROL_PASS_IRQ_EN_MASK) >> MTG_TRA_CMD_CONTROL_PASS_IRQ_EN_SHIFT)

/*
 * MODE (RW)
 *
 */
#define MTG_TRA_CMD_CONTROL_MODE_MASK (0x20000000UL)
#define MTG_TRA_CMD_CONTROL_MODE_SHIFT (29U)
#define MTG_TRA_CMD_CONTROL_MODE_SET(x) (((uint32_t)(x) << MTG_TRA_CMD_CONTROL_MODE_SHIFT) & MTG_TRA_CMD_CONTROL_MODE_MASK)
#define MTG_TRA_CMD_CONTROL_MODE_GET(x) (((uint32_t)(x) & MTG_TRA_CMD_CONTROL_MODE_MASK) >> MTG_TRA_CMD_CONTROL_MODE_SHIFT)

/*
 * OBJECT (RW)
 *
 */
#define MTG_TRA_CMD_CONTROL_OBJECT_MASK (0x1FU)
#define MTG_TRA_CMD_CONTROL_OBJECT_SHIFT (0U)
#define MTG_TRA_CMD_CONTROL_OBJECT_SET(x) (((uint32_t)(x) << MTG_TRA_CMD_CONTROL_OBJECT_SHIFT) & MTG_TRA_CMD_CONTROL_OBJECT_MASK)
#define MTG_TRA_CMD_CONTROL_OBJECT_GET(x) (((uint32_t)(x) & MTG_TRA_CMD_CONTROL_OBJECT_MASK) >> MTG_TRA_CMD_CONTROL_OBJECT_SHIFT)

/* Bitfield definition for register of struct array TRA: REV_PRESET */
/*
 * REV_PRESET (RW)
 *
 */
#define MTG_TRA_CMD_REV_PRESET_REV_PRESET_MASK (0xFFFFFFFFUL)
#define MTG_TRA_CMD_REV_PRESET_REV_PRESET_SHIFT (0U)
#define MTG_TRA_CMD_REV_PRESET_REV_PRESET_SET(x) (((uint32_t)(x) << MTG_TRA_CMD_REV_PRESET_REV_PRESET_SHIFT) & MTG_TRA_CMD_REV_PRESET_REV_PRESET_MASK)
#define MTG_TRA_CMD_REV_PRESET_REV_PRESET_GET(x) (((uint32_t)(x) & MTG_TRA_CMD_REV_PRESET_REV_PRESET_MASK) >> MTG_TRA_CMD_REV_PRESET_REV_PRESET_SHIFT)

/* Bitfield definition for register of struct array TRA: POS_PRESET */
/*
 * POS_PRESET (RW)
 *
 */
#define MTG_TRA_CMD_POS_PRESET_POS_PRESET_MASK (0xFFFFFFFFUL)
#define MTG_TRA_CMD_POS_PRESET_POS_PRESET_SHIFT (0U)
#define MTG_TRA_CMD_POS_PRESET_POS_PRESET_SET(x) (((uint32_t)(x) << MTG_TRA_CMD_POS_PRESET_POS_PRESET_SHIFT) & MTG_TRA_CMD_POS_PRESET_POS_PRESET_MASK)
#define MTG_TRA_CMD_POS_PRESET_POS_PRESET_GET(x) (((uint32_t)(x) & MTG_TRA_CMD_POS_PRESET_POS_PRESET_MASK) >> MTG_TRA_CMD_POS_PRESET_POS_PRESET_SHIFT)

/* Bitfield definition for register of struct array TRA: VEL_PRESET */
/*
 * VEL_PRESET (RW)
 *
 */
#define MTG_TRA_CMD_VEL_PRESET_VEL_PRESET_MASK (0xFFFFFFFFUL)
#define MTG_TRA_CMD_VEL_PRESET_VEL_PRESET_SHIFT (0U)
#define MTG_TRA_CMD_VEL_PRESET_VEL_PRESET_SET(x) (((uint32_t)(x) << MTG_TRA_CMD_VEL_PRESET_VEL_PRESET_SHIFT) & MTG_TRA_CMD_VEL_PRESET_VEL_PRESET_MASK)
#define MTG_TRA_CMD_VEL_PRESET_VEL_PRESET_GET(x) (((uint32_t)(x) & MTG_TRA_CMD_VEL_PRESET_VEL_PRESET_MASK) >> MTG_TRA_CMD_VEL_PRESET_VEL_PRESET_SHIFT)

/* Bitfield definition for register of struct array TRA: ACC_PRESET */
/*
 * ACC_PRESET (RW)
 *
 */
#define MTG_TRA_CMD_ACC_PRESET_ACC_PRESET_MASK (0xFFFFFFFFUL)
#define MTG_TRA_CMD_ACC_PRESET_ACC_PRESET_SHIFT (0U)
#define MTG_TRA_CMD_ACC_PRESET_ACC_PRESET_SET(x) (((uint32_t)(x) << MTG_TRA_CMD_ACC_PRESET_ACC_PRESET_SHIFT) & MTG_TRA_CMD_ACC_PRESET_ACC_PRESET_MASK)
#define MTG_TRA_CMD_ACC_PRESET_ACC_PRESET_GET(x) (((uint32_t)(x) & MTG_TRA_CMD_ACC_PRESET_ACC_PRESET_MASK) >> MTG_TRA_CMD_ACC_PRESET_ACC_PRESET_SHIFT)

/* Bitfield definition for register of struct array TRA: JER_PRESET */
/*
 * JER_PRESET (RW)
 *
 */
#define MTG_TRA_CMD_JER_PRESET_JER_PRESET_MASK (0xFFFFFFFFUL)
#define MTG_TRA_CMD_JER_PRESET_JER_PRESET_SHIFT (0U)
#define MTG_TRA_CMD_JER_PRESET_JER_PRESET_SET(x) (((uint32_t)(x) << MTG_TRA_CMD_JER_PRESET_JER_PRESET_SHIFT) & MTG_TRA_CMD_JER_PRESET_JER_PRESET_MASK)
#define MTG_TRA_CMD_JER_PRESET_JER_PRESET_GET(x) (((uint32_t)(x) & MTG_TRA_CMD_JER_PRESET_JER_PRESET_MASK) >> MTG_TRA_CMD_JER_PRESET_JER_PRESET_SHIFT)

/* Bitfield definition for register of struct array TRA: TIMESTAMP */
/*
 * TIMESTAMP (RO)
 *
 */
#define MTG_TRA_CMD_TIMESTAMP_TIMESTAMP_MASK (0xFFFFFFFFUL)
#define MTG_TRA_CMD_TIMESTAMP_TIMESTAMP_SHIFT (0U)
#define MTG_TRA_CMD_TIMESTAMP_TIMESTAMP_GET(x) (((uint32_t)(x) & MTG_TRA_CMD_TIMESTAMP_TIMESTAMP_MASK) >> MTG_TRA_CMD_TIMESTAMP_TIMESTAMP_SHIFT)

/* Bitfield definition for register of struct array TRA: LOCK_REV */
/*
 * LOCK_REV (RO)
 *
 */
#define MTG_TRA_LOCK_REV_LOCK_REV_MASK (0xFFFFFFFFUL)
#define MTG_TRA_LOCK_REV_LOCK_REV_SHIFT (0U)
#define MTG_TRA_LOCK_REV_LOCK_REV_GET(x) (((uint32_t)(x) & MTG_TRA_LOCK_REV_LOCK_REV_MASK) >> MTG_TRA_LOCK_REV_LOCK_REV_SHIFT)

/* Bitfield definition for register of struct array TRA: LOCK_POS */
/*
 * LOCK_POS (RO)
 *
 */
#define MTG_TRA_LOCK_POS_LOCK_POS_MASK (0xFFFFFFFFUL)
#define MTG_TRA_LOCK_POS_LOCK_POS_SHIFT (0U)
#define MTG_TRA_LOCK_POS_LOCK_POS_GET(x) (((uint32_t)(x) & MTG_TRA_LOCK_POS_LOCK_POS_MASK) >> MTG_TRA_LOCK_POS_LOCK_POS_SHIFT)

/* Bitfield definition for register of struct array TRA: LOCK_VEL */
/*
 * LOCK_VEL (RO)
 *
 */
#define MTG_TRA_LOCK_VEL_LOCK_VEL_MASK (0xFFFFFFFFUL)
#define MTG_TRA_LOCK_VEL_LOCK_VEL_SHIFT (0U)
#define MTG_TRA_LOCK_VEL_LOCK_VEL_GET(x) (((uint32_t)(x) & MTG_TRA_LOCK_VEL_LOCK_VEL_MASK) >> MTG_TRA_LOCK_VEL_LOCK_VEL_SHIFT)

/* Bitfield definition for register of struct array TRA: LOCK_ACC */
/*
 * LOCK_ACC (RO)
 *
 */
#define MTG_TRA_LOCK_ACC_LOCK_ACC_MASK (0xFFFFFFFFUL)
#define MTG_TRA_LOCK_ACC_LOCK_ACC_SHIFT (0U)
#define MTG_TRA_LOCK_ACC_LOCK_ACC_GET(x) (((uint32_t)(x) & MTG_TRA_LOCK_ACC_LOCK_ACC_MASK) >> MTG_TRA_LOCK_ACC_LOCK_ACC_SHIFT)

/* Bitfield definition for register of struct array TRA: LOCK_TIME */
/*
 * LOCK_TIME (RO)
 *
 */
#define MTG_TRA_LOCK_TIME_LOCK_TIME_MASK (0xFFFFFFFFUL)
#define MTG_TRA_LOCK_TIME_LOCK_TIME_SHIFT (0U)
#define MTG_TRA_LOCK_TIME_LOCK_TIME_GET(x) (((uint32_t)(x) & MTG_TRA_LOCK_TIME_LOCK_TIME_MASK) >> MTG_TRA_LOCK_TIME_LOCK_TIME_SHIFT)

/* Bitfield definition for register of struct array TRA: STEP_LIMIT_CTRL */
/*
 * POS_ONE_WAY_FORCE_MODE (RW)
 *
 */
#define MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_FORCE_MODE_MASK (0x1000U)
#define MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_FORCE_MODE_SHIFT (12U)
#define MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_FORCE_MODE_SET(x) (((uint32_t)(x) << MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_FORCE_MODE_SHIFT) & MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_FORCE_MODE_MASK)
#define MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_FORCE_MODE_GET(x) (((uint32_t)(x) & MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_FORCE_MODE_MASK) >> MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_FORCE_MODE_SHIFT)

/*
 * POS_ONE_WAY_MODE (RW)
 *
 */
#define MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_MODE_MASK (0x800U)
#define MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_MODE_SHIFT (11U)
#define MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_MODE_SET(x) (((uint32_t)(x) << MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_MODE_SHIFT) & MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_MODE_MASK)
#define MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_MODE_GET(x) (((uint32_t)(x) & MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_MODE_MASK) >> MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_MODE_SHIFT)

/*
 * POS_ONE_WAY_EN (RW)
 *
 */
#define MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_EN_MASK (0x400U)
#define MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_EN_SHIFT (10U)
#define MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_EN_SET(x) (((uint32_t)(x) << MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_EN_SHIFT) & MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_EN_MASK)
#define MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_EN_GET(x) (((uint32_t)(x) & MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_EN_MASK) >> MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_EN_SHIFT)

/*
 * POS_STEP_MODE (RW)
 *
 */
#define MTG_TRA_STEP_LIMIT_CTRL_POS_STEP_MODE_MASK (0x200U)
#define MTG_TRA_STEP_LIMIT_CTRL_POS_STEP_MODE_SHIFT (9U)
#define MTG_TRA_STEP_LIMIT_CTRL_POS_STEP_MODE_SET(x) (((uint32_t)(x) << MTG_TRA_STEP_LIMIT_CTRL_POS_STEP_MODE_SHIFT) & MTG_TRA_STEP_LIMIT_CTRL_POS_STEP_MODE_MASK)
#define MTG_TRA_STEP_LIMIT_CTRL_POS_STEP_MODE_GET(x) (((uint32_t)(x) & MTG_TRA_STEP_LIMIT_CTRL_POS_STEP_MODE_MASK) >> MTG_TRA_STEP_LIMIT_CTRL_POS_STEP_MODE_SHIFT)

/*
 * POS_STEP_EN (RW)
 *
 */
#define MTG_TRA_STEP_LIMIT_CTRL_POS_STEP_EN_MASK (0x100U)
#define MTG_TRA_STEP_LIMIT_CTRL_POS_STEP_EN_SHIFT (8U)
#define MTG_TRA_STEP_LIMIT_CTRL_POS_STEP_EN_SET(x) (((uint32_t)(x) << MTG_TRA_STEP_LIMIT_CTRL_POS_STEP_EN_SHIFT) & MTG_TRA_STEP_LIMIT_CTRL_POS_STEP_EN_MASK)
#define MTG_TRA_STEP_LIMIT_CTRL_POS_STEP_EN_GET(x) (((uint32_t)(x) & MTG_TRA_STEP_LIMIT_CTRL_POS_STEP_EN_MASK) >> MTG_TRA_STEP_LIMIT_CTRL_POS_STEP_EN_SHIFT)

/*
 * VEL_ONE_WAY_MODE (RW)
 *
 */
#define MTG_TRA_STEP_LIMIT_CTRL_VEL_ONE_WAY_MODE_MASK (0x4U)
#define MTG_TRA_STEP_LIMIT_CTRL_VEL_ONE_WAY_MODE_SHIFT (2U)
#define MTG_TRA_STEP_LIMIT_CTRL_VEL_ONE_WAY_MODE_SET(x) (((uint32_t)(x) << MTG_TRA_STEP_LIMIT_CTRL_VEL_ONE_WAY_MODE_SHIFT) & MTG_TRA_STEP_LIMIT_CTRL_VEL_ONE_WAY_MODE_MASK)
#define MTG_TRA_STEP_LIMIT_CTRL_VEL_ONE_WAY_MODE_GET(x) (((uint32_t)(x) & MTG_TRA_STEP_LIMIT_CTRL_VEL_ONE_WAY_MODE_MASK) >> MTG_TRA_STEP_LIMIT_CTRL_VEL_ONE_WAY_MODE_SHIFT)

/*
 * VEL_ONE_WAY_EN (RW)
 *
 */
#define MTG_TRA_STEP_LIMIT_CTRL_VEL_ONE_WAY_EN_MASK (0x2U)
#define MTG_TRA_STEP_LIMIT_CTRL_VEL_ONE_WAY_EN_SHIFT (1U)
#define MTG_TRA_STEP_LIMIT_CTRL_VEL_ONE_WAY_EN_SET(x) (((uint32_t)(x) << MTG_TRA_STEP_LIMIT_CTRL_VEL_ONE_WAY_EN_SHIFT) & MTG_TRA_STEP_LIMIT_CTRL_VEL_ONE_WAY_EN_MASK)
#define MTG_TRA_STEP_LIMIT_CTRL_VEL_ONE_WAY_EN_GET(x) (((uint32_t)(x) & MTG_TRA_STEP_LIMIT_CTRL_VEL_ONE_WAY_EN_MASK) >> MTG_TRA_STEP_LIMIT_CTRL_VEL_ONE_WAY_EN_SHIFT)

/*
 * VEL_STEP_EN (RW)
 *
 */
#define MTG_TRA_STEP_LIMIT_CTRL_VEL_STEP_EN_MASK (0x1U)
#define MTG_TRA_STEP_LIMIT_CTRL_VEL_STEP_EN_SHIFT (0U)
#define MTG_TRA_STEP_LIMIT_CTRL_VEL_STEP_EN_SET(x) (((uint32_t)(x) << MTG_TRA_STEP_LIMIT_CTRL_VEL_STEP_EN_SHIFT) & MTG_TRA_STEP_LIMIT_CTRL_VEL_STEP_EN_MASK)
#define MTG_TRA_STEP_LIMIT_CTRL_VEL_STEP_EN_GET(x) (((uint32_t)(x) & MTG_TRA_STEP_LIMIT_CTRL_VEL_STEP_EN_MASK) >> MTG_TRA_STEP_LIMIT_CTRL_VEL_STEP_EN_SHIFT)

/* Bitfield definition for register of struct array TRA: VEL_STEP_MAX */
/*
 * VEL_STEP_MAX (RW)
 *
 */
#define MTG_TRA_VEL_STEP_MAX_VEL_STEP_MAX_MASK (0xFFFFFFFFUL)
#define MTG_TRA_VEL_STEP_MAX_VEL_STEP_MAX_SHIFT (0U)
#define MTG_TRA_VEL_STEP_MAX_VEL_STEP_MAX_SET(x) (((uint32_t)(x) << MTG_TRA_VEL_STEP_MAX_VEL_STEP_MAX_SHIFT) & MTG_TRA_VEL_STEP_MAX_VEL_STEP_MAX_MASK)
#define MTG_TRA_VEL_STEP_MAX_VEL_STEP_MAX_GET(x) (((uint32_t)(x) & MTG_TRA_VEL_STEP_MAX_VEL_STEP_MAX_MASK) >> MTG_TRA_VEL_STEP_MAX_VEL_STEP_MAX_SHIFT)

/* Bitfield definition for register of struct array TRA: VEL_STEP_MIN */
/*
 * VEL_STEP_MIN (RW)
 *
 */
#define MTG_TRA_VEL_STEP_MIN_VEL_STEP_MIN_MASK (0xFFFFFFFFUL)
#define MTG_TRA_VEL_STEP_MIN_VEL_STEP_MIN_SHIFT (0U)
#define MTG_TRA_VEL_STEP_MIN_VEL_STEP_MIN_SET(x) (((uint32_t)(x) << MTG_TRA_VEL_STEP_MIN_VEL_STEP_MIN_SHIFT) & MTG_TRA_VEL_STEP_MIN_VEL_STEP_MIN_MASK)
#define MTG_TRA_VEL_STEP_MIN_VEL_STEP_MIN_GET(x) (((uint32_t)(x) & MTG_TRA_VEL_STEP_MIN_VEL_STEP_MIN_MASK) >> MTG_TRA_VEL_STEP_MIN_VEL_STEP_MIN_SHIFT)

/* Bitfield definition for register of struct array TRA: POS_STEP_MAX */
/*
 * POS_STEP_MAX (RW)
 *
 */
#define MTG_TRA_POS_STEP_MAX_POS_STEP_MAX_MASK (0xFFFFFFFFUL)
#define MTG_TRA_POS_STEP_MAX_POS_STEP_MAX_SHIFT (0U)
#define MTG_TRA_POS_STEP_MAX_POS_STEP_MAX_SET(x) (((uint32_t)(x) << MTG_TRA_POS_STEP_MAX_POS_STEP_MAX_SHIFT) & MTG_TRA_POS_STEP_MAX_POS_STEP_MAX_MASK)
#define MTG_TRA_POS_STEP_MAX_POS_STEP_MAX_GET(x) (((uint32_t)(x) & MTG_TRA_POS_STEP_MAX_POS_STEP_MAX_MASK) >> MTG_TRA_POS_STEP_MAX_POS_STEP_MAX_SHIFT)

/* Bitfield definition for register of struct array TRA: POS_STEP_MIN */
/*
 * POS_STEP_MIN (RW)
 *
 */
#define MTG_TRA_POS_STEP_MIN_POS_STEP_MIN_MASK (0xFFFFFFFFUL)
#define MTG_TRA_POS_STEP_MIN_POS_STEP_MIN_SHIFT (0U)
#define MTG_TRA_POS_STEP_MIN_POS_STEP_MIN_SET(x) (((uint32_t)(x) << MTG_TRA_POS_STEP_MIN_POS_STEP_MIN_SHIFT) & MTG_TRA_POS_STEP_MIN_POS_STEP_MIN_MASK)
#define MTG_TRA_POS_STEP_MIN_POS_STEP_MIN_GET(x) (((uint32_t)(x) & MTG_TRA_POS_STEP_MIN_POS_STEP_MIN_MASK) >> MTG_TRA_POS_STEP_MIN_POS_STEP_MIN_SHIFT)

/* Bitfield definition for register of struct array TRA: VEL_LIMIT_P */
/*
 * VEL_LIMIT_P (RW)
 *
 */
#define MTG_TRA_VEL_LIMIT_P_VEL_LIMIT_P_MASK (0xFFFFFFFFUL)
#define MTG_TRA_VEL_LIMIT_P_VEL_LIMIT_P_SHIFT (0U)
#define MTG_TRA_VEL_LIMIT_P_VEL_LIMIT_P_SET(x) (((uint32_t)(x) << MTG_TRA_VEL_LIMIT_P_VEL_LIMIT_P_SHIFT) & MTG_TRA_VEL_LIMIT_P_VEL_LIMIT_P_MASK)
#define MTG_TRA_VEL_LIMIT_P_VEL_LIMIT_P_GET(x) (((uint32_t)(x) & MTG_TRA_VEL_LIMIT_P_VEL_LIMIT_P_MASK) >> MTG_TRA_VEL_LIMIT_P_VEL_LIMIT_P_SHIFT)

/* Bitfield definition for register of struct array TRA: VEL_LIMIT_N */
/*
 * VEL_LIMIT_N (RW)
 *
 */
#define MTG_TRA_VEL_LIMIT_N_VEL_LIMIT_N_MASK (0xFFFFFFFFUL)
#define MTG_TRA_VEL_LIMIT_N_VEL_LIMIT_N_SHIFT (0U)
#define MTG_TRA_VEL_LIMIT_N_VEL_LIMIT_N_SET(x) (((uint32_t)(x) << MTG_TRA_VEL_LIMIT_N_VEL_LIMIT_N_SHIFT) & MTG_TRA_VEL_LIMIT_N_VEL_LIMIT_N_MASK)
#define MTG_TRA_VEL_LIMIT_N_VEL_LIMIT_N_GET(x) (((uint32_t)(x) & MTG_TRA_VEL_LIMIT_N_VEL_LIMIT_N_MASK) >> MTG_TRA_VEL_LIMIT_N_VEL_LIMIT_N_SHIFT)

/* Bitfield definition for register of struct array EVENT: CONTROL */
/*
 * ENABLE (RW)
 *
 */
#define MTG_EVENT_CONTROL_ENABLE_MASK (0x80000000UL)
#define MTG_EVENT_CONTROL_ENABLE_SHIFT (31U)
#define MTG_EVENT_CONTROL_ENABLE_SET(x) (((uint32_t)(x) << MTG_EVENT_CONTROL_ENABLE_SHIFT) & MTG_EVENT_CONTROL_ENABLE_MASK)
#define MTG_EVENT_CONTROL_ENABLE_GET(x) (((uint32_t)(x) & MTG_EVENT_CONTROL_ENABLE_MASK) >> MTG_EVENT_CONTROL_ENABLE_SHIFT)

/*
 * SOURCE_MUX (RW)
 *
 */
#define MTG_EVENT_CONTROL_SOURCE_MUX_MASK (0x78000000UL)
#define MTG_EVENT_CONTROL_SOURCE_MUX_SHIFT (27U)
#define MTG_EVENT_CONTROL_SOURCE_MUX_SET(x) (((uint32_t)(x) << MTG_EVENT_CONTROL_SOURCE_MUX_SHIFT) & MTG_EVENT_CONTROL_SOURCE_MUX_MASK)
#define MTG_EVENT_CONTROL_SOURCE_MUX_GET(x) (((uint32_t)(x) & MTG_EVENT_CONTROL_SOURCE_MUX_MASK) >> MTG_EVENT_CONTROL_SOURCE_MUX_SHIFT)

/*
 * OBJECT (RW)
 *
 */
#define MTG_EVENT_CONTROL_OBJECT_MASK (0x7800000UL)
#define MTG_EVENT_CONTROL_OBJECT_SHIFT (23U)
#define MTG_EVENT_CONTROL_OBJECT_SET(x) (((uint32_t)(x) << MTG_EVENT_CONTROL_OBJECT_SHIFT) & MTG_EVENT_CONTROL_OBJECT_MASK)
#define MTG_EVENT_CONTROL_OBJECT_GET(x) (((uint32_t)(x) & MTG_EVENT_CONTROL_OBJECT_MASK) >> MTG_EVENT_CONTROL_OBJECT_SHIFT)

/*
 * MODE (RW)
 *
 */
#define MTG_EVENT_CONTROL_MODE_MASK (0x780000UL)
#define MTG_EVENT_CONTROL_MODE_SHIFT (19U)
#define MTG_EVENT_CONTROL_MODE_SET(x) (((uint32_t)(x) << MTG_EVENT_CONTROL_MODE_SHIFT) & MTG_EVENT_CONTROL_MODE_MASK)
#define MTG_EVENT_CONTROL_MODE_GET(x) (((uint32_t)(x) & MTG_EVENT_CONTROL_MODE_MASK) >> MTG_EVENT_CONTROL_MODE_SHIFT)

/*
 * DIR (RW)
 *
 */
#define MTG_EVENT_CONTROL_DIR_MASK (0x60000UL)
#define MTG_EVENT_CONTROL_DIR_SHIFT (17U)
#define MTG_EVENT_CONTROL_DIR_SET(x) (((uint32_t)(x) << MTG_EVENT_CONTROL_DIR_SHIFT) & MTG_EVENT_CONTROL_DIR_MASK)
#define MTG_EVENT_CONTROL_DIR_GET(x) (((uint32_t)(x) & MTG_EVENT_CONTROL_DIR_MASK) >> MTG_EVENT_CONTROL_DIR_SHIFT)

/*
 * DIR_MODE (RW)
 *
 */
#define MTG_EVENT_CONTROL_DIR_MODE_MASK (0x10000UL)
#define MTG_EVENT_CONTROL_DIR_MODE_SHIFT (16U)
#define MTG_EVENT_CONTROL_DIR_MODE_SET(x) (((uint32_t)(x) << MTG_EVENT_CONTROL_DIR_MODE_SHIFT) & MTG_EVENT_CONTROL_DIR_MODE_MASK)
#define MTG_EVENT_CONTROL_DIR_MODE_GET(x) (((uint32_t)(x) & MTG_EVENT_CONTROL_DIR_MODE_MASK) >> MTG_EVENT_CONTROL_DIR_MODE_SHIFT)

/*
 * OVER_MODE_CMP (RW)
 *
 */
#define MTG_EVENT_CONTROL_OVER_MODE_CMP_MASK (0x8000U)
#define MTG_EVENT_CONTROL_OVER_MODE_CMP_SHIFT (15U)
#define MTG_EVENT_CONTROL_OVER_MODE_CMP_SET(x) (((uint32_t)(x) << MTG_EVENT_CONTROL_OVER_MODE_CMP_SHIFT) & MTG_EVENT_CONTROL_OVER_MODE_CMP_MASK)
#define MTG_EVENT_CONTROL_OVER_MODE_CMP_GET(x) (((uint32_t)(x) & MTG_EVENT_CONTROL_OVER_MODE_CMP_MASK) >> MTG_EVENT_CONTROL_OVER_MODE_CMP_SHIFT)

/*
 * TRIG_NUM (RW)
 *
 */
#define MTG_EVENT_CONTROL_TRIG_NUM_MASK (0x4000U)
#define MTG_EVENT_CONTROL_TRIG_NUM_SHIFT (14U)
#define MTG_EVENT_CONTROL_TRIG_NUM_SET(x) (((uint32_t)(x) << MTG_EVENT_CONTROL_TRIG_NUM_SHIFT) & MTG_EVENT_CONTROL_TRIG_NUM_MASK)
#define MTG_EVENT_CONTROL_TRIG_NUM_GET(x) (((uint32_t)(x) & MTG_EVENT_CONTROL_TRIG_NUM_MASK) >> MTG_EVENT_CONTROL_TRIG_NUM_SHIFT)

/*
 * EVENT_OVER_IRQ_EN (RW)
 *
 */
#define MTG_EVENT_CONTROL_EVENT_OVER_IRQ_EN_MASK (0x8U)
#define MTG_EVENT_CONTROL_EVENT_OVER_IRQ_EN_SHIFT (3U)
#define MTG_EVENT_CONTROL_EVENT_OVER_IRQ_EN_SET(x) (((uint32_t)(x) << MTG_EVENT_CONTROL_EVENT_OVER_IRQ_EN_SHIFT) & MTG_EVENT_CONTROL_EVENT_OVER_IRQ_EN_MASK)
#define MTG_EVENT_CONTROL_EVENT_OVER_IRQ_EN_GET(x) (((uint32_t)(x) & MTG_EVENT_CONTROL_EVENT_OVER_IRQ_EN_MASK) >> MTG_EVENT_CONTROL_EVENT_OVER_IRQ_EN_SHIFT)

/*
 * EVENT_IRQ_EN (RW)
 *
 */
#define MTG_EVENT_CONTROL_EVENT_IRQ_EN_MASK (0x4U)
#define MTG_EVENT_CONTROL_EVENT_IRQ_EN_SHIFT (2U)
#define MTG_EVENT_CONTROL_EVENT_IRQ_EN_SET(x) (((uint32_t)(x) << MTG_EVENT_CONTROL_EVENT_IRQ_EN_SHIFT) & MTG_EVENT_CONTROL_EVENT_IRQ_EN_MASK)
#define MTG_EVENT_CONTROL_EVENT_IRQ_EN_GET(x) (((uint32_t)(x) & MTG_EVENT_CONTROL_EVENT_IRQ_EN_MASK) >> MTG_EVENT_CONTROL_EVENT_IRQ_EN_SHIFT)

/*
 * EVENT_OVER_IRQ (W1C)
 *
 */
#define MTG_EVENT_CONTROL_EVENT_OVER_IRQ_MASK (0x2U)
#define MTG_EVENT_CONTROL_EVENT_OVER_IRQ_SHIFT (1U)
#define MTG_EVENT_CONTROL_EVENT_OVER_IRQ_SET(x) (((uint32_t)(x) << MTG_EVENT_CONTROL_EVENT_OVER_IRQ_SHIFT) & MTG_EVENT_CONTROL_EVENT_OVER_IRQ_MASK)
#define MTG_EVENT_CONTROL_EVENT_OVER_IRQ_GET(x) (((uint32_t)(x) & MTG_EVENT_CONTROL_EVENT_OVER_IRQ_MASK) >> MTG_EVENT_CONTROL_EVENT_OVER_IRQ_SHIFT)

/*
 * EVENT_IRQ (W1C)
 *
 */
#define MTG_EVENT_CONTROL_EVENT_IRQ_MASK (0x1U)
#define MTG_EVENT_CONTROL_EVENT_IRQ_SHIFT (0U)
#define MTG_EVENT_CONTROL_EVENT_IRQ_SET(x) (((uint32_t)(x) << MTG_EVENT_CONTROL_EVENT_IRQ_SHIFT) & MTG_EVENT_CONTROL_EVENT_IRQ_MASK)
#define MTG_EVENT_CONTROL_EVENT_IRQ_GET(x) (((uint32_t)(x) & MTG_EVENT_CONTROL_EVENT_IRQ_MASK) >> MTG_EVENT_CONTROL_EVENT_IRQ_SHIFT)

/* Bitfield definition for register of struct array EVENT: PRESET_0 */
/*
 * PRESET (RW)
 *
 */
#define MTG_EVENT_PRESET_0_PRESET_MASK (0xFFFFFFFFUL)
#define MTG_EVENT_PRESET_0_PRESET_SHIFT (0U)
#define MTG_EVENT_PRESET_0_PRESET_SET(x) (((uint32_t)(x) << MTG_EVENT_PRESET_0_PRESET_SHIFT) & MTG_EVENT_PRESET_0_PRESET_MASK)
#define MTG_EVENT_PRESET_0_PRESET_GET(x) (((uint32_t)(x) & MTG_EVENT_PRESET_0_PRESET_MASK) >> MTG_EVENT_PRESET_0_PRESET_SHIFT)

/* Bitfield definition for register of struct array EVENT: PRESET_1 */
/*
 * PRESET (RW)
 *
 */
#define MTG_EVENT_PRESET_1_PRESET_MASK (0xFFFFFFFFUL)
#define MTG_EVENT_PRESET_1_PRESET_SHIFT (0U)
#define MTG_EVENT_PRESET_1_PRESET_SET(x) (((uint32_t)(x) << MTG_EVENT_PRESET_1_PRESET_SHIFT) & MTG_EVENT_PRESET_1_PRESET_MASK)
#define MTG_EVENT_PRESET_1_PRESET_GET(x) (((uint32_t)(x) & MTG_EVENT_PRESET_1_PRESET_MASK) >> MTG_EVENT_PRESET_1_PRESET_SHIFT)

/* Bitfield definition for register of struct array EVENT: PRESET_2 */
/*
 * PRESET (RW)
 *
 */
#define MTG_EVENT_PRESET_2_PRESET_MASK (0xFFFFFFFFUL)
#define MTG_EVENT_PRESET_2_PRESET_SHIFT (0U)
#define MTG_EVENT_PRESET_2_PRESET_SET(x) (((uint32_t)(x) << MTG_EVENT_PRESET_2_PRESET_SHIFT) & MTG_EVENT_PRESET_2_PRESET_MASK)
#define MTG_EVENT_PRESET_2_PRESET_GET(x) (((uint32_t)(x) & MTG_EVENT_PRESET_2_PRESET_MASK) >> MTG_EVENT_PRESET_2_PRESET_SHIFT)

/* Bitfield definition for register of struct array EVENT: PRESET_3 */
/*
 * PRESET (RW)
 *
 */
#define MTG_EVENT_PRESET_3_PRESET_MASK (0xFFFFFFFFUL)
#define MTG_EVENT_PRESET_3_PRESET_SHIFT (0U)
#define MTG_EVENT_PRESET_3_PRESET_SET(x) (((uint32_t)(x) << MTG_EVENT_PRESET_3_PRESET_SHIFT) & MTG_EVENT_PRESET_3_PRESET_MASK)
#define MTG_EVENT_PRESET_3_PRESET_GET(x) (((uint32_t)(x) & MTG_EVENT_PRESET_3_PRESET_MASK) >> MTG_EVENT_PRESET_3_PRESET_SHIFT)

/* Bitfield definition for register of struct array EVENT: TIMESTAMP */
/*
 * TIMESTAMP (RO)
 *
 */
#define MTG_EVENT_TIMESTAMP_TIMESTAMP_MASK (0xFFFFFFFFUL)
#define MTG_EVENT_TIMESTAMP_TIMESTAMP_SHIFT (0U)
#define MTG_EVENT_TIMESTAMP_TIMESTAMP_GET(x) (((uint32_t)(x) & MTG_EVENT_TIMESTAMP_TIMESTAMP_MASK) >> MTG_EVENT_TIMESTAMP_TIMESTAMP_SHIFT)

/* Bitfield definition for register: SW_EVENT */
/*
 * SW_EVENT_TRIG (RW)
 *
 */
#define MTG_SW_EVENT_SW_EVENT_TRIG_MASK (0x1U)
#define MTG_SW_EVENT_SW_EVENT_TRIG_SHIFT (0U)
#define MTG_SW_EVENT_SW_EVENT_TRIG_SET(x) (((uint32_t)(x) << MTG_SW_EVENT_SW_EVENT_TRIG_SHIFT) & MTG_SW_EVENT_SW_EVENT_TRIG_MASK)
#define MTG_SW_EVENT_SW_EVENT_TRIG_GET(x) (((uint32_t)(x) & MTG_SW_EVENT_SW_EVENT_TRIG_MASK) >> MTG_SW_EVENT_SW_EVENT_TRIG_SHIFT)

/* Bitfield definition for register: SW_GLB_RESET */
/*
 * SW_GLB_RESET (WO)
 *
 */
#define MTG_SW_GLB_RESET_SW_GLB_RESET_MASK (0x1U)
#define MTG_SW_GLB_RESET_SW_GLB_RESET_SHIFT (0U)
#define MTG_SW_GLB_RESET_SW_GLB_RESET_SET(x) (((uint32_t)(x) << MTG_SW_GLB_RESET_SW_GLB_RESET_SHIFT) & MTG_SW_GLB_RESET_SW_GLB_RESET_MASK)
#define MTG_SW_GLB_RESET_SW_GLB_RESET_GET(x) (((uint32_t)(x) & MTG_SW_GLB_RESET_SW_GLB_RESET_MASK) >> MTG_SW_GLB_RESET_SW_GLB_RESET_SHIFT)

/* Bitfield definition for register: FILTER_CONTROL */
/*
 * MUL_ERR_IRQ_0 (W1C)
 *
 */
#define MTG_FILTER_CONTROL_MUL_ERR_IRQ_0_MASK (0x80000000UL)
#define MTG_FILTER_CONTROL_MUL_ERR_IRQ_0_SHIFT (31U)
#define MTG_FILTER_CONTROL_MUL_ERR_IRQ_0_SET(x) (((uint32_t)(x) << MTG_FILTER_CONTROL_MUL_ERR_IRQ_0_SHIFT) & MTG_FILTER_CONTROL_MUL_ERR_IRQ_0_MASK)
#define MTG_FILTER_CONTROL_MUL_ERR_IRQ_0_GET(x) (((uint32_t)(x) & MTG_FILTER_CONTROL_MUL_ERR_IRQ_0_MASK) >> MTG_FILTER_CONTROL_MUL_ERR_IRQ_0_SHIFT)

/*
 * MUL_ERR_IRQ_1 (W1C)
 *
 */
#define MTG_FILTER_CONTROL_MUL_ERR_IRQ_1_MASK (0x40000000UL)
#define MTG_FILTER_CONTROL_MUL_ERR_IRQ_1_SHIFT (30U)
#define MTG_FILTER_CONTROL_MUL_ERR_IRQ_1_SET(x) (((uint32_t)(x) << MTG_FILTER_CONTROL_MUL_ERR_IRQ_1_SHIFT) & MTG_FILTER_CONTROL_MUL_ERR_IRQ_1_MASK)
#define MTG_FILTER_CONTROL_MUL_ERR_IRQ_1_GET(x) (((uint32_t)(x) & MTG_FILTER_CONTROL_MUL_ERR_IRQ_1_MASK) >> MTG_FILTER_CONTROL_MUL_ERR_IRQ_1_SHIFT)

/*
 * MUL_ERR_IRQ_EN (RW)
 *
 */
#define MTG_FILTER_CONTROL_MUL_ERR_IRQ_EN_MASK (0x20000000UL)
#define MTG_FILTER_CONTROL_MUL_ERR_IRQ_EN_SHIFT (29U)
#define MTG_FILTER_CONTROL_MUL_ERR_IRQ_EN_SET(x) (((uint32_t)(x) << MTG_FILTER_CONTROL_MUL_ERR_IRQ_EN_SHIFT) & MTG_FILTER_CONTROL_MUL_ERR_IRQ_EN_MASK)
#define MTG_FILTER_CONTROL_MUL_ERR_IRQ_EN_GET(x) (((uint32_t)(x) & MTG_FILTER_CONTROL_MUL_ERR_IRQ_EN_MASK) >> MTG_FILTER_CONTROL_MUL_ERR_IRQ_EN_SHIFT)

/*
 * ERR_BYPASS_STATUS (RO)
 *
 */
#define MTG_FILTER_CONTROL_ERR_BYPASS_STATUS_MASK (0x800000UL)
#define MTG_FILTER_CONTROL_ERR_BYPASS_STATUS_SHIFT (23U)
#define MTG_FILTER_CONTROL_ERR_BYPASS_STATUS_GET(x) (((uint32_t)(x) & MTG_FILTER_CONTROL_ERR_BYPASS_STATUS_MASK) >> MTG_FILTER_CONTROL_ERR_BYPASS_STATUS_SHIFT)

/*
 * ERR_BYPASS_F_I_EN (RW)
 *
 */
#define MTG_FILTER_CONTROL_ERR_BYPASS_F_I_EN_MASK (0x400000UL)
#define MTG_FILTER_CONTROL_ERR_BYPASS_F_I_EN_SHIFT (22U)
#define MTG_FILTER_CONTROL_ERR_BYPASS_F_I_EN_SET(x) (((uint32_t)(x) << MTG_FILTER_CONTROL_ERR_BYPASS_F_I_EN_SHIFT) & MTG_FILTER_CONTROL_ERR_BYPASS_F_I_EN_MASK)
#define MTG_FILTER_CONTROL_ERR_BYPASS_F_I_EN_GET(x) (((uint32_t)(x) & MTG_FILTER_CONTROL_ERR_BYPASS_F_I_EN_MASK) >> MTG_FILTER_CONTROL_ERR_BYPASS_F_I_EN_SHIFT)

/*
 * ERR_BYPASS_I_F_EN (RW)
 *
 */
#define MTG_FILTER_CONTROL_ERR_BYPASS_I_F_EN_MASK (0x200000UL)
#define MTG_FILTER_CONTROL_ERR_BYPASS_I_F_EN_SHIFT (21U)
#define MTG_FILTER_CONTROL_ERR_BYPASS_I_F_EN_SET(x) (((uint32_t)(x) << MTG_FILTER_CONTROL_ERR_BYPASS_I_F_EN_SHIFT) & MTG_FILTER_CONTROL_ERR_BYPASS_I_F_EN_MASK)
#define MTG_FILTER_CONTROL_ERR_BYPASS_I_F_EN_GET(x) (((uint32_t)(x) & MTG_FILTER_CONTROL_ERR_BYPASS_I_F_EN_MASK) >> MTG_FILTER_CONTROL_ERR_BYPASS_I_F_EN_SHIFT)

/*
 * SW_LOCK (RW)
 *
 */
#define MTG_FILTER_CONTROL_SW_LOCK_MASK (0x100000UL)
#define MTG_FILTER_CONTROL_SW_LOCK_SHIFT (20U)
#define MTG_FILTER_CONTROL_SW_LOCK_SET(x) (((uint32_t)(x) << MTG_FILTER_CONTROL_SW_LOCK_SHIFT) & MTG_FILTER_CONTROL_SW_LOCK_MASK)
#define MTG_FILTER_CONTROL_SW_LOCK_GET(x) (((uint32_t)(x) & MTG_FILTER_CONTROL_SW_LOCK_MASK) >> MTG_FILTER_CONTROL_SW_LOCK_SHIFT)

/*
 * TIMEOUT_EN (RW)
 *
 */
#define MTG_FILTER_CONTROL_TIMEOUT_EN_MASK (0x80000UL)
#define MTG_FILTER_CONTROL_TIMEOUT_EN_SHIFT (19U)
#define MTG_FILTER_CONTROL_TIMEOUT_EN_SET(x) (((uint32_t)(x) << MTG_FILTER_CONTROL_TIMEOUT_EN_SHIFT) & MTG_FILTER_CONTROL_TIMEOUT_EN_MASK)
#define MTG_FILTER_CONTROL_TIMEOUT_EN_GET(x) (((uint32_t)(x) & MTG_FILTER_CONTROL_TIMEOUT_EN_MASK) >> MTG_FILTER_CONTROL_TIMEOUT_EN_SHIFT)

/*
 * REV_INI_MODE (RW)
 *
 */
#define MTG_FILTER_CONTROL_REV_INI_MODE_MASK (0x20000UL)
#define MTG_FILTER_CONTROL_REV_INI_MODE_SHIFT (17U)
#define MTG_FILTER_CONTROL_REV_INI_MODE_SET(x) (((uint32_t)(x) << MTG_FILTER_CONTROL_REV_INI_MODE_SHIFT) & MTG_FILTER_CONTROL_REV_INI_MODE_MASK)
#define MTG_FILTER_CONTROL_REV_INI_MODE_GET(x) (((uint32_t)(x) & MTG_FILTER_CONTROL_REV_INI_MODE_MASK) >> MTG_FILTER_CONTROL_REV_INI_MODE_SHIFT)

/*
 * SEL_TIME1 (RW)
 *
 */
#define MTG_FILTER_CONTROL_SEL_TIME1_MASK (0x3000U)
#define MTG_FILTER_CONTROL_SEL_TIME1_SHIFT (12U)
#define MTG_FILTER_CONTROL_SEL_TIME1_SET(x) (((uint32_t)(x) << MTG_FILTER_CONTROL_SEL_TIME1_SHIFT) & MTG_FILTER_CONTROL_SEL_TIME1_MASK)
#define MTG_FILTER_CONTROL_SEL_TIME1_GET(x) (((uint32_t)(x) & MTG_FILTER_CONTROL_SEL_TIME1_MASK) >> MTG_FILTER_CONTROL_SEL_TIME1_SHIFT)

/*
 * SEL_TIME0 (RW)
 *
 */
#define MTG_FILTER_CONTROL_SEL_TIME0_MASK (0xC00U)
#define MTG_FILTER_CONTROL_SEL_TIME0_SHIFT (10U)
#define MTG_FILTER_CONTROL_SEL_TIME0_SET(x) (((uint32_t)(x) << MTG_FILTER_CONTROL_SEL_TIME0_SHIFT) & MTG_FILTER_CONTROL_SEL_TIME0_MASK)
#define MTG_FILTER_CONTROL_SEL_TIME0_GET(x) (((uint32_t)(x) & MTG_FILTER_CONTROL_SEL_TIME0_MASK) >> MTG_FILTER_CONTROL_SEL_TIME0_SHIFT)

/*
 * EN_TIME1 (RW)
 *
 */
#define MTG_FILTER_CONTROL_EN_TIME1_MASK (0x200U)
#define MTG_FILTER_CONTROL_EN_TIME1_SHIFT (9U)
#define MTG_FILTER_CONTROL_EN_TIME1_SET(x) (((uint32_t)(x) << MTG_FILTER_CONTROL_EN_TIME1_SHIFT) & MTG_FILTER_CONTROL_EN_TIME1_MASK)
#define MTG_FILTER_CONTROL_EN_TIME1_GET(x) (((uint32_t)(x) & MTG_FILTER_CONTROL_EN_TIME1_MASK) >> MTG_FILTER_CONTROL_EN_TIME1_SHIFT)

/*
 * EN_TIME0 (RW)
 *
 */
#define MTG_FILTER_CONTROL_EN_TIME0_MASK (0x100U)
#define MTG_FILTER_CONTROL_EN_TIME0_SHIFT (8U)
#define MTG_FILTER_CONTROL_EN_TIME0_SET(x) (((uint32_t)(x) << MTG_FILTER_CONTROL_EN_TIME0_SHIFT) & MTG_FILTER_CONTROL_EN_TIME0_MASK)
#define MTG_FILTER_CONTROL_EN_TIME0_GET(x) (((uint32_t)(x) & MTG_FILTER_CONTROL_EN_TIME0_MASK) >> MTG_FILTER_CONTROL_EN_TIME0_SHIFT)

/*
 * A_EN (RW)
 *
 */
#define MTG_FILTER_CONTROL_A_EN_MASK (0x40U)
#define MTG_FILTER_CONTROL_A_EN_SHIFT (6U)
#define MTG_FILTER_CONTROL_A_EN_SET(x) (((uint32_t)(x) << MTG_FILTER_CONTROL_A_EN_SHIFT) & MTG_FILTER_CONTROL_A_EN_MASK)
#define MTG_FILTER_CONTROL_A_EN_GET(x) (((uint32_t)(x) & MTG_FILTER_CONTROL_A_EN_MASK) >> MTG_FILTER_CONTROL_A_EN_SHIFT)

/*
 * ERR_INI (RW)
 *
 */
#define MTG_FILTER_CONTROL_ERR_INI_MASK (0x20U)
#define MTG_FILTER_CONTROL_ERR_INI_SHIFT (5U)
#define MTG_FILTER_CONTROL_ERR_INI_SET(x) (((uint32_t)(x) << MTG_FILTER_CONTROL_ERR_INI_SHIFT) & MTG_FILTER_CONTROL_ERR_INI_MASK)
#define MTG_FILTER_CONTROL_ERR_INI_GET(x) (((uint32_t)(x) & MTG_FILTER_CONTROL_ERR_INI_MASK) >> MTG_FILTER_CONTROL_ERR_INI_SHIFT)

/*
 * ERR_BYPASS_EN (RW)
 *
 */
#define MTG_FILTER_CONTROL_ERR_BYPASS_EN_MASK (0x10U)
#define MTG_FILTER_CONTROL_ERR_BYPASS_EN_SHIFT (4U)
#define MTG_FILTER_CONTROL_ERR_BYPASS_EN_SET(x) (((uint32_t)(x) << MTG_FILTER_CONTROL_ERR_BYPASS_EN_SHIFT) & MTG_FILTER_CONTROL_ERR_BYPASS_EN_MASK)
#define MTG_FILTER_CONTROL_ERR_BYPASS_EN_GET(x) (((uint32_t)(x) & MTG_FILTER_CONTROL_ERR_BYPASS_EN_MASK) >> MTG_FILTER_CONTROL_ERR_BYPASS_EN_SHIFT)

/*
 * FF_MODE (RW)
 *
 */
#define MTG_FILTER_CONTROL_FF_MODE_MASK (0x8U)
#define MTG_FILTER_CONTROL_FF_MODE_SHIFT (3U)
#define MTG_FILTER_CONTROL_FF_MODE_SET(x) (((uint32_t)(x) << MTG_FILTER_CONTROL_FF_MODE_SHIFT) & MTG_FILTER_CONTROL_FF_MODE_MASK)
#define MTG_FILTER_CONTROL_FF_MODE_GET(x) (((uint32_t)(x) & MTG_FILTER_CONTROL_FF_MODE_MASK) >> MTG_FILTER_CONTROL_FF_MODE_SHIFT)

/*
 * FF_EN (RW)
 *
 */
#define MTG_FILTER_CONTROL_FF_EN_MASK (0x4U)
#define MTG_FILTER_CONTROL_FF_EN_SHIFT (2U)
#define MTG_FILTER_CONTROL_FF_EN_SET(x) (((uint32_t)(x) << MTG_FILTER_CONTROL_FF_EN_SHIFT) & MTG_FILTER_CONTROL_FF_EN_MASK)
#define MTG_FILTER_CONTROL_FF_EN_GET(x) (((uint32_t)(x) & MTG_FILTER_CONTROL_FF_EN_MASK) >> MTG_FILTER_CONTROL_FF_EN_SHIFT)

/*
 * INIT_EN (RW)
 *
 */
#define MTG_FILTER_CONTROL_INIT_EN_MASK (0x2U)
#define MTG_FILTER_CONTROL_INIT_EN_SHIFT (1U)
#define MTG_FILTER_CONTROL_INIT_EN_SET(x) (((uint32_t)(x) << MTG_FILTER_CONTROL_INIT_EN_SHIFT) & MTG_FILTER_CONTROL_INIT_EN_MASK)
#define MTG_FILTER_CONTROL_INIT_EN_GET(x) (((uint32_t)(x) & MTG_FILTER_CONTROL_INIT_EN_MASK) >> MTG_FILTER_CONTROL_INIT_EN_SHIFT)

/*
 * ENABLE (RW)
 *
 */
#define MTG_FILTER_CONTROL_ENABLE_MASK (0x1U)
#define MTG_FILTER_CONTROL_ENABLE_SHIFT (0U)
#define MTG_FILTER_CONTROL_ENABLE_SET(x) (((uint32_t)(x) << MTG_FILTER_CONTROL_ENABLE_SHIFT) & MTG_FILTER_CONTROL_ENABLE_MASK)
#define MTG_FILTER_CONTROL_ENABLE_GET(x) (((uint32_t)(x) & MTG_FILTER_CONTROL_ENABLE_MASK) >> MTG_FILTER_CONTROL_ENABLE_SHIFT)

/* Bitfield definition for register: FILTER_REV_VALUE */
/*
 * VALUE (RW)
 *
 */
#define MTG_FILTER_REV_VALUE_VALUE_MASK (0xFFFFFFFFUL)
#define MTG_FILTER_REV_VALUE_VALUE_SHIFT (0U)
#define MTG_FILTER_REV_VALUE_VALUE_SET(x) (((uint32_t)(x) << MTG_FILTER_REV_VALUE_VALUE_SHIFT) & MTG_FILTER_REV_VALUE_VALUE_MASK)
#define MTG_FILTER_REV_VALUE_VALUE_GET(x) (((uint32_t)(x) & MTG_FILTER_REV_VALUE_VALUE_MASK) >> MTG_FILTER_REV_VALUE_VALUE_SHIFT)

/* Bitfield definition for register: FILTER_POS_VALUE */
/*
 * VALUE (RW)
 *
 */
#define MTG_FILTER_POS_VALUE_VALUE_MASK (0xFFFFFFFFUL)
#define MTG_FILTER_POS_VALUE_VALUE_SHIFT (0U)
#define MTG_FILTER_POS_VALUE_VALUE_SET(x) (((uint32_t)(x) << MTG_FILTER_POS_VALUE_VALUE_SHIFT) & MTG_FILTER_POS_VALUE_VALUE_MASK)
#define MTG_FILTER_POS_VALUE_VALUE_GET(x) (((uint32_t)(x) & MTG_FILTER_POS_VALUE_VALUE_MASK) >> MTG_FILTER_POS_VALUE_VALUE_SHIFT)

/* Bitfield definition for register: FILTER_VEL_VALUE */
/*
 * VALUE (RW)
 *
 */
#define MTG_FILTER_VEL_VALUE_VALUE_MASK (0xFFFFFFFFUL)
#define MTG_FILTER_VEL_VALUE_VALUE_SHIFT (0U)
#define MTG_FILTER_VEL_VALUE_VALUE_SET(x) (((uint32_t)(x) << MTG_FILTER_VEL_VALUE_VALUE_SHIFT) & MTG_FILTER_VEL_VALUE_VALUE_MASK)
#define MTG_FILTER_VEL_VALUE_VALUE_GET(x) (((uint32_t)(x) & MTG_FILTER_VEL_VALUE_VALUE_MASK) >> MTG_FILTER_VEL_VALUE_VALUE_SHIFT)

/* Bitfield definition for register: FILTER_ACC_VALUE */
/*
 * VALUE (RW)
 *
 */
#define MTG_FILTER_ACC_VALUE_VALUE_MASK (0xFFFFFFFFUL)
#define MTG_FILTER_ACC_VALUE_VALUE_SHIFT (0U)
#define MTG_FILTER_ACC_VALUE_VALUE_SET(x) (((uint32_t)(x) << MTG_FILTER_ACC_VALUE_VALUE_SHIFT) & MTG_FILTER_ACC_VALUE_VALUE_MASK)
#define MTG_FILTER_ACC_VALUE_VALUE_GET(x) (((uint32_t)(x) & MTG_FILTER_ACC_VALUE_VALUE_MASK) >> MTG_FILTER_ACC_VALUE_VALUE_SHIFT)

/* Bitfield definition for register: FILTER_MOT_SEL */
/*
 * OUTPUT_VEL_SEL (RW)
 *
 */
#define MTG_FILTER_MOT_SEL_OUTPUT_VEL_SEL_MASK (0x3F000000UL)
#define MTG_FILTER_MOT_SEL_OUTPUT_VEL_SEL_SHIFT (24U)
#define MTG_FILTER_MOT_SEL_OUTPUT_VEL_SEL_SET(x) (((uint32_t)(x) << MTG_FILTER_MOT_SEL_OUTPUT_VEL_SEL_SHIFT) & MTG_FILTER_MOT_SEL_OUTPUT_VEL_SEL_MASK)
#define MTG_FILTER_MOT_SEL_OUTPUT_VEL_SEL_GET(x) (((uint32_t)(x) & MTG_FILTER_MOT_SEL_OUTPUT_VEL_SEL_MASK) >> MTG_FILTER_MOT_SEL_OUTPUT_VEL_SEL_SHIFT)

/*
 * OUTPUT_ACC_SEL (RW)
 *
 */
#define MTG_FILTER_MOT_SEL_OUTPUT_ACC_SEL_MASK (0x3F0000UL)
#define MTG_FILTER_MOT_SEL_OUTPUT_ACC_SEL_SHIFT (16U)
#define MTG_FILTER_MOT_SEL_OUTPUT_ACC_SEL_SET(x) (((uint32_t)(x) << MTG_FILTER_MOT_SEL_OUTPUT_ACC_SEL_SHIFT) & MTG_FILTER_MOT_SEL_OUTPUT_ACC_SEL_MASK)
#define MTG_FILTER_MOT_SEL_OUTPUT_ACC_SEL_GET(x) (((uint32_t)(x) & MTG_FILTER_MOT_SEL_OUTPUT_ACC_SEL_MASK) >> MTG_FILTER_MOT_SEL_OUTPUT_ACC_SEL_SHIFT)

/*
 * FILTER_VEL_SEL (RW)
 *
 */
#define MTG_FILTER_MOT_SEL_FILTER_VEL_SEL_MASK (0x3F00U)
#define MTG_FILTER_MOT_SEL_FILTER_VEL_SEL_SHIFT (8U)
#define MTG_FILTER_MOT_SEL_FILTER_VEL_SEL_SET(x) (((uint32_t)(x) << MTG_FILTER_MOT_SEL_FILTER_VEL_SEL_SHIFT) & MTG_FILTER_MOT_SEL_FILTER_VEL_SEL_MASK)
#define MTG_FILTER_MOT_SEL_FILTER_VEL_SEL_GET(x) (((uint32_t)(x) & MTG_FILTER_MOT_SEL_FILTER_VEL_SEL_MASK) >> MTG_FILTER_MOT_SEL_FILTER_VEL_SEL_SHIFT)

/*
 * FILTER_ACC_SEL (RW)
 *
 */
#define MTG_FILTER_MOT_SEL_FILTER_ACC_SEL_MASK (0x3FU)
#define MTG_FILTER_MOT_SEL_FILTER_ACC_SEL_SHIFT (0U)
#define MTG_FILTER_MOT_SEL_FILTER_ACC_SEL_SET(x) (((uint32_t)(x) << MTG_FILTER_MOT_SEL_FILTER_ACC_SEL_SHIFT) & MTG_FILTER_MOT_SEL_FILTER_ACC_SEL_MASK)
#define MTG_FILTER_MOT_SEL_FILTER_ACC_SEL_GET(x) (((uint32_t)(x) & MTG_FILTER_MOT_SEL_FILTER_ACC_SEL_MASK) >> MTG_FILTER_MOT_SEL_FILTER_ACC_SEL_SHIFT)

/* Bitfield definition for register: FILTER_STAGE_SEL */
/*
 * STAGE5_SEL (RW)
 *
 */
#define MTG_FILTER_STAGE_SEL_STAGE5_SEL_MASK (0x3E000000UL)
#define MTG_FILTER_STAGE_SEL_STAGE5_SEL_SHIFT (25U)
#define MTG_FILTER_STAGE_SEL_STAGE5_SEL_SET(x) (((uint32_t)(x) << MTG_FILTER_STAGE_SEL_STAGE5_SEL_SHIFT) & MTG_FILTER_STAGE_SEL_STAGE5_SEL_MASK)
#define MTG_FILTER_STAGE_SEL_STAGE5_SEL_GET(x) (((uint32_t)(x) & MTG_FILTER_STAGE_SEL_STAGE5_SEL_MASK) >> MTG_FILTER_STAGE_SEL_STAGE5_SEL_SHIFT)

/*
 * STAGE4_SEL (RW)
 *
 */
#define MTG_FILTER_STAGE_SEL_STAGE4_SEL_MASK (0x1F00000UL)
#define MTG_FILTER_STAGE_SEL_STAGE4_SEL_SHIFT (20U)
#define MTG_FILTER_STAGE_SEL_STAGE4_SEL_SET(x) (((uint32_t)(x) << MTG_FILTER_STAGE_SEL_STAGE4_SEL_SHIFT) & MTG_FILTER_STAGE_SEL_STAGE4_SEL_MASK)
#define MTG_FILTER_STAGE_SEL_STAGE4_SEL_GET(x) (((uint32_t)(x) & MTG_FILTER_STAGE_SEL_STAGE4_SEL_MASK) >> MTG_FILTER_STAGE_SEL_STAGE4_SEL_SHIFT)

/*
 * STAGE3_SEL (RW)
 *
 */
#define MTG_FILTER_STAGE_SEL_STAGE3_SEL_MASK (0xF8000UL)
#define MTG_FILTER_STAGE_SEL_STAGE3_SEL_SHIFT (15U)
#define MTG_FILTER_STAGE_SEL_STAGE3_SEL_SET(x) (((uint32_t)(x) << MTG_FILTER_STAGE_SEL_STAGE3_SEL_SHIFT) & MTG_FILTER_STAGE_SEL_STAGE3_SEL_MASK)
#define MTG_FILTER_STAGE_SEL_STAGE3_SEL_GET(x) (((uint32_t)(x) & MTG_FILTER_STAGE_SEL_STAGE3_SEL_MASK) >> MTG_FILTER_STAGE_SEL_STAGE3_SEL_SHIFT)

/*
 * STAGE2_SEL (RW)
 *
 */
#define MTG_FILTER_STAGE_SEL_STAGE2_SEL_MASK (0x7C00U)
#define MTG_FILTER_STAGE_SEL_STAGE2_SEL_SHIFT (10U)
#define MTG_FILTER_STAGE_SEL_STAGE2_SEL_SET(x) (((uint32_t)(x) << MTG_FILTER_STAGE_SEL_STAGE2_SEL_SHIFT) & MTG_FILTER_STAGE_SEL_STAGE2_SEL_MASK)
#define MTG_FILTER_STAGE_SEL_STAGE2_SEL_GET(x) (((uint32_t)(x) & MTG_FILTER_STAGE_SEL_STAGE2_SEL_MASK) >> MTG_FILTER_STAGE_SEL_STAGE2_SEL_SHIFT)

/*
 * STAGE1_SEL (RW)
 *
 */
#define MTG_FILTER_STAGE_SEL_STAGE1_SEL_MASK (0x3E0U)
#define MTG_FILTER_STAGE_SEL_STAGE1_SEL_SHIFT (5U)
#define MTG_FILTER_STAGE_SEL_STAGE1_SEL_SET(x) (((uint32_t)(x) << MTG_FILTER_STAGE_SEL_STAGE1_SEL_SHIFT) & MTG_FILTER_STAGE_SEL_STAGE1_SEL_MASK)
#define MTG_FILTER_STAGE_SEL_STAGE1_SEL_GET(x) (((uint32_t)(x) & MTG_FILTER_STAGE_SEL_STAGE1_SEL_MASK) >> MTG_FILTER_STAGE_SEL_STAGE1_SEL_SHIFT)

/*
 * STAGE0_SEL (RW)
 *
 */
#define MTG_FILTER_STAGE_SEL_STAGE0_SEL_MASK (0x1FU)
#define MTG_FILTER_STAGE_SEL_STAGE0_SEL_SHIFT (0U)
#define MTG_FILTER_STAGE_SEL_STAGE0_SEL_SET(x) (((uint32_t)(x) << MTG_FILTER_STAGE_SEL_STAGE0_SEL_SHIFT) & MTG_FILTER_STAGE_SEL_STAGE0_SEL_MASK)
#define MTG_FILTER_STAGE_SEL_STAGE0_SEL_GET(x) (((uint32_t)(x) & MTG_FILTER_STAGE_SEL_STAGE0_SEL_MASK) >> MTG_FILTER_STAGE_SEL_STAGE0_SEL_SHIFT)

/* Bitfield definition for register: FILTER_TIME_CONSTANT_TP */
/*
 * TP (RW)
 *
 */
#define MTG_FILTER_TIME_CONSTANT_TP_TP_MASK (0xFFFFFFUL)
#define MTG_FILTER_TIME_CONSTANT_TP_TP_SHIFT (0U)
#define MTG_FILTER_TIME_CONSTANT_TP_TP_SET(x) (((uint32_t)(x) << MTG_FILTER_TIME_CONSTANT_TP_TP_SHIFT) & MTG_FILTER_TIME_CONSTANT_TP_TP_MASK)
#define MTG_FILTER_TIME_CONSTANT_TP_TP_GET(x) (((uint32_t)(x) & MTG_FILTER_TIME_CONSTANT_TP_TP_MASK) >> MTG_FILTER_TIME_CONSTANT_TP_TP_SHIFT)

/* Bitfield definition for register: FILTER_TIME_CONSTANT_TZ */
/*
 * TZ (RW)
 *
 */
#define MTG_FILTER_TIME_CONSTANT_TZ_TZ_MASK (0xFFFFFFUL)
#define MTG_FILTER_TIME_CONSTANT_TZ_TZ_SHIFT (0U)
#define MTG_FILTER_TIME_CONSTANT_TZ_TZ_SET(x) (((uint32_t)(x) << MTG_FILTER_TIME_CONSTANT_TZ_TZ_SHIFT) & MTG_FILTER_TIME_CONSTANT_TZ_TZ_MASK)
#define MTG_FILTER_TIME_CONSTANT_TZ_TZ_GET(x) (((uint32_t)(x) & MTG_FILTER_TIME_CONSTANT_TZ_TZ_MASK) >> MTG_FILTER_TIME_CONSTANT_TZ_TZ_SHIFT)

/* Bitfield definition for register: FILTER_TIME_CONSTANT_TZ_1 */
/*
 * TZ_1 (RW)
 *
 */
#define MTG_FILTER_TIME_CONSTANT_TZ_1_TZ_1_MASK (0xFFFFFFUL)
#define MTG_FILTER_TIME_CONSTANT_TZ_1_TZ_1_SHIFT (0U)
#define MTG_FILTER_TIME_CONSTANT_TZ_1_TZ_1_SET(x) (((uint32_t)(x) << MTG_FILTER_TIME_CONSTANT_TZ_1_TZ_1_SHIFT) & MTG_FILTER_TIME_CONSTANT_TZ_1_TZ_1_MASK)
#define MTG_FILTER_TIME_CONSTANT_TZ_1_TZ_1_GET(x) (((uint32_t)(x) & MTG_FILTER_TIME_CONSTANT_TZ_1_TZ_1_MASK) >> MTG_FILTER_TIME_CONSTANT_TZ_1_TZ_1_SHIFT)

/* Bitfield definition for register: FILTER_ZERO_TZ_SEL */
/*
 * STAGE5 (RW)
 *
 */
#define MTG_FILTER_ZERO_TZ_SEL_STAGE5_MASK (0x20U)
#define MTG_FILTER_ZERO_TZ_SEL_STAGE5_SHIFT (5U)
#define MTG_FILTER_ZERO_TZ_SEL_STAGE5_SET(x) (((uint32_t)(x) << MTG_FILTER_ZERO_TZ_SEL_STAGE5_SHIFT) & MTG_FILTER_ZERO_TZ_SEL_STAGE5_MASK)
#define MTG_FILTER_ZERO_TZ_SEL_STAGE5_GET(x) (((uint32_t)(x) & MTG_FILTER_ZERO_TZ_SEL_STAGE5_MASK) >> MTG_FILTER_ZERO_TZ_SEL_STAGE5_SHIFT)

/*
 * STAGE4 (RW)
 *
 */
#define MTG_FILTER_ZERO_TZ_SEL_STAGE4_MASK (0x10U)
#define MTG_FILTER_ZERO_TZ_SEL_STAGE4_SHIFT (4U)
#define MTG_FILTER_ZERO_TZ_SEL_STAGE4_SET(x) (((uint32_t)(x) << MTG_FILTER_ZERO_TZ_SEL_STAGE4_SHIFT) & MTG_FILTER_ZERO_TZ_SEL_STAGE4_MASK)
#define MTG_FILTER_ZERO_TZ_SEL_STAGE4_GET(x) (((uint32_t)(x) & MTG_FILTER_ZERO_TZ_SEL_STAGE4_MASK) >> MTG_FILTER_ZERO_TZ_SEL_STAGE4_SHIFT)

/*
 * STAGE3 (RW)
 *
 */
#define MTG_FILTER_ZERO_TZ_SEL_STAGE3_MASK (0x8U)
#define MTG_FILTER_ZERO_TZ_SEL_STAGE3_SHIFT (3U)
#define MTG_FILTER_ZERO_TZ_SEL_STAGE3_SET(x) (((uint32_t)(x) << MTG_FILTER_ZERO_TZ_SEL_STAGE3_SHIFT) & MTG_FILTER_ZERO_TZ_SEL_STAGE3_MASK)
#define MTG_FILTER_ZERO_TZ_SEL_STAGE3_GET(x) (((uint32_t)(x) & MTG_FILTER_ZERO_TZ_SEL_STAGE3_MASK) >> MTG_FILTER_ZERO_TZ_SEL_STAGE3_SHIFT)

/*
 * STAGE2 (RW)
 *
 */
#define MTG_FILTER_ZERO_TZ_SEL_STAGE2_MASK (0x4U)
#define MTG_FILTER_ZERO_TZ_SEL_STAGE2_SHIFT (2U)
#define MTG_FILTER_ZERO_TZ_SEL_STAGE2_SET(x) (((uint32_t)(x) << MTG_FILTER_ZERO_TZ_SEL_STAGE2_SHIFT) & MTG_FILTER_ZERO_TZ_SEL_STAGE2_MASK)
#define MTG_FILTER_ZERO_TZ_SEL_STAGE2_GET(x) (((uint32_t)(x) & MTG_FILTER_ZERO_TZ_SEL_STAGE2_MASK) >> MTG_FILTER_ZERO_TZ_SEL_STAGE2_SHIFT)

/*
 * STAGE1 (RW)
 *
 */
#define MTG_FILTER_ZERO_TZ_SEL_STAGE1_MASK (0x2U)
#define MTG_FILTER_ZERO_TZ_SEL_STAGE1_SHIFT (1U)
#define MTG_FILTER_ZERO_TZ_SEL_STAGE1_SET(x) (((uint32_t)(x) << MTG_FILTER_ZERO_TZ_SEL_STAGE1_SHIFT) & MTG_FILTER_ZERO_TZ_SEL_STAGE1_MASK)
#define MTG_FILTER_ZERO_TZ_SEL_STAGE1_GET(x) (((uint32_t)(x) & MTG_FILTER_ZERO_TZ_SEL_STAGE1_MASK) >> MTG_FILTER_ZERO_TZ_SEL_STAGE1_SHIFT)

/*
 * STAGE0 (RW)
 *
 */
#define MTG_FILTER_ZERO_TZ_SEL_STAGE0_MASK (0x1U)
#define MTG_FILTER_ZERO_TZ_SEL_STAGE0_SHIFT (0U)
#define MTG_FILTER_ZERO_TZ_SEL_STAGE0_SET(x) (((uint32_t)(x) << MTG_FILTER_ZERO_TZ_SEL_STAGE0_SHIFT) & MTG_FILTER_ZERO_TZ_SEL_STAGE0_MASK)
#define MTG_FILTER_ZERO_TZ_SEL_STAGE0_GET(x) (((uint32_t)(x) & MTG_FILTER_ZERO_TZ_SEL_STAGE0_MASK) >> MTG_FILTER_ZERO_TZ_SEL_STAGE0_SHIFT)

/* Bitfield definition for register: FILTER_GAIN */
/*
 * GAIN_T0_EN (RW)
 *
 */
#define MTG_FILTER_GAIN_GAIN_T0_EN_MASK (0x80000000UL)
#define MTG_FILTER_GAIN_GAIN_T0_EN_SHIFT (31U)
#define MTG_FILTER_GAIN_GAIN_T0_EN_SET(x) (((uint32_t)(x) << MTG_FILTER_GAIN_GAIN_T0_EN_SHIFT) & MTG_FILTER_GAIN_GAIN_T0_EN_MASK)
#define MTG_FILTER_GAIN_GAIN_T0_EN_GET(x) (((uint32_t)(x) & MTG_FILTER_GAIN_GAIN_T0_EN_MASK) >> MTG_FILTER_GAIN_GAIN_T0_EN_SHIFT)

/*
 * GAIN_T1_EN (RW)
 *
 */
#define MTG_FILTER_GAIN_GAIN_T1_EN_MASK (0x40000000UL)
#define MTG_FILTER_GAIN_GAIN_T1_EN_SHIFT (30U)
#define MTG_FILTER_GAIN_GAIN_T1_EN_SET(x) (((uint32_t)(x) << MTG_FILTER_GAIN_GAIN_T1_EN_SHIFT) & MTG_FILTER_GAIN_GAIN_T1_EN_MASK)
#define MTG_FILTER_GAIN_GAIN_T1_EN_GET(x) (((uint32_t)(x) & MTG_FILTER_GAIN_GAIN_T1_EN_MASK) >> MTG_FILTER_GAIN_GAIN_T1_EN_SHIFT)

/*
 * K (RW)
 *
 */
#define MTG_FILTER_GAIN_K_MASK (0xFFFFFFUL)
#define MTG_FILTER_GAIN_K_SHIFT (0U)
#define MTG_FILTER_GAIN_K_SET(x) (((uint32_t)(x) << MTG_FILTER_GAIN_K_SHIFT) & MTG_FILTER_GAIN_K_MASK)
#define MTG_FILTER_GAIN_K_GET(x) (((uint32_t)(x) & MTG_FILTER_GAIN_K_MASK) >> MTG_FILTER_GAIN_K_SHIFT)

/* Bitfield definition for register: FILTER_STAGE_SHIFT0 */
/*
 * STAGE3_SHIFT1 (RW)
 *
 */
#define MTG_FILTER_STAGE_SHIFT0_STAGE3_SHIFT1_MASK (0xF0000000UL)
#define MTG_FILTER_STAGE_SHIFT0_STAGE3_SHIFT1_SHIFT (28U)
#define MTG_FILTER_STAGE_SHIFT0_STAGE3_SHIFT1_SET(x) (((uint32_t)(x) << MTG_FILTER_STAGE_SHIFT0_STAGE3_SHIFT1_SHIFT) & MTG_FILTER_STAGE_SHIFT0_STAGE3_SHIFT1_MASK)
#define MTG_FILTER_STAGE_SHIFT0_STAGE3_SHIFT1_GET(x) (((uint32_t)(x) & MTG_FILTER_STAGE_SHIFT0_STAGE3_SHIFT1_MASK) >> MTG_FILTER_STAGE_SHIFT0_STAGE3_SHIFT1_SHIFT)

/*
 * STAGE3_SHIFT0 (RW)
 *
 */
#define MTG_FILTER_STAGE_SHIFT0_STAGE3_SHIFT0_MASK (0xF000000UL)
#define MTG_FILTER_STAGE_SHIFT0_STAGE3_SHIFT0_SHIFT (24U)
#define MTG_FILTER_STAGE_SHIFT0_STAGE3_SHIFT0_SET(x) (((uint32_t)(x) << MTG_FILTER_STAGE_SHIFT0_STAGE3_SHIFT0_SHIFT) & MTG_FILTER_STAGE_SHIFT0_STAGE3_SHIFT0_MASK)
#define MTG_FILTER_STAGE_SHIFT0_STAGE3_SHIFT0_GET(x) (((uint32_t)(x) & MTG_FILTER_STAGE_SHIFT0_STAGE3_SHIFT0_MASK) >> MTG_FILTER_STAGE_SHIFT0_STAGE3_SHIFT0_SHIFT)

/*
 * STAGE2_SHIFT1 (RW)
 *
 */
#define MTG_FILTER_STAGE_SHIFT0_STAGE2_SHIFT1_MASK (0xF00000UL)
#define MTG_FILTER_STAGE_SHIFT0_STAGE2_SHIFT1_SHIFT (20U)
#define MTG_FILTER_STAGE_SHIFT0_STAGE2_SHIFT1_SET(x) (((uint32_t)(x) << MTG_FILTER_STAGE_SHIFT0_STAGE2_SHIFT1_SHIFT) & MTG_FILTER_STAGE_SHIFT0_STAGE2_SHIFT1_MASK)
#define MTG_FILTER_STAGE_SHIFT0_STAGE2_SHIFT1_GET(x) (((uint32_t)(x) & MTG_FILTER_STAGE_SHIFT0_STAGE2_SHIFT1_MASK) >> MTG_FILTER_STAGE_SHIFT0_STAGE2_SHIFT1_SHIFT)

/*
 * STAGE2_SHIFT0 (RW)
 *
 */
#define MTG_FILTER_STAGE_SHIFT0_STAGE2_SHIFT0_MASK (0xF0000UL)
#define MTG_FILTER_STAGE_SHIFT0_STAGE2_SHIFT0_SHIFT (16U)
#define MTG_FILTER_STAGE_SHIFT0_STAGE2_SHIFT0_SET(x) (((uint32_t)(x) << MTG_FILTER_STAGE_SHIFT0_STAGE2_SHIFT0_SHIFT) & MTG_FILTER_STAGE_SHIFT0_STAGE2_SHIFT0_MASK)
#define MTG_FILTER_STAGE_SHIFT0_STAGE2_SHIFT0_GET(x) (((uint32_t)(x) & MTG_FILTER_STAGE_SHIFT0_STAGE2_SHIFT0_MASK) >> MTG_FILTER_STAGE_SHIFT0_STAGE2_SHIFT0_SHIFT)

/*
 * STAGE1_SHIFT1 (RW)
 *
 */
#define MTG_FILTER_STAGE_SHIFT0_STAGE1_SHIFT1_MASK (0xF000U)
#define MTG_FILTER_STAGE_SHIFT0_STAGE1_SHIFT1_SHIFT (12U)
#define MTG_FILTER_STAGE_SHIFT0_STAGE1_SHIFT1_SET(x) (((uint32_t)(x) << MTG_FILTER_STAGE_SHIFT0_STAGE1_SHIFT1_SHIFT) & MTG_FILTER_STAGE_SHIFT0_STAGE1_SHIFT1_MASK)
#define MTG_FILTER_STAGE_SHIFT0_STAGE1_SHIFT1_GET(x) (((uint32_t)(x) & MTG_FILTER_STAGE_SHIFT0_STAGE1_SHIFT1_MASK) >> MTG_FILTER_STAGE_SHIFT0_STAGE1_SHIFT1_SHIFT)

/*
 * STAGE1_SHIFT0 (RW)
 *
 */
#define MTG_FILTER_STAGE_SHIFT0_STAGE1_SHIFT0_MASK (0xF00U)
#define MTG_FILTER_STAGE_SHIFT0_STAGE1_SHIFT0_SHIFT (8U)
#define MTG_FILTER_STAGE_SHIFT0_STAGE1_SHIFT0_SET(x) (((uint32_t)(x) << MTG_FILTER_STAGE_SHIFT0_STAGE1_SHIFT0_SHIFT) & MTG_FILTER_STAGE_SHIFT0_STAGE1_SHIFT0_MASK)
#define MTG_FILTER_STAGE_SHIFT0_STAGE1_SHIFT0_GET(x) (((uint32_t)(x) & MTG_FILTER_STAGE_SHIFT0_STAGE1_SHIFT0_MASK) >> MTG_FILTER_STAGE_SHIFT0_STAGE1_SHIFT0_SHIFT)

/*
 * STAGE0_SHIFT1 (RW)
 *
 */
#define MTG_FILTER_STAGE_SHIFT0_STAGE0_SHIFT1_MASK (0xF0U)
#define MTG_FILTER_STAGE_SHIFT0_STAGE0_SHIFT1_SHIFT (4U)
#define MTG_FILTER_STAGE_SHIFT0_STAGE0_SHIFT1_SET(x) (((uint32_t)(x) << MTG_FILTER_STAGE_SHIFT0_STAGE0_SHIFT1_SHIFT) & MTG_FILTER_STAGE_SHIFT0_STAGE0_SHIFT1_MASK)
#define MTG_FILTER_STAGE_SHIFT0_STAGE0_SHIFT1_GET(x) (((uint32_t)(x) & MTG_FILTER_STAGE_SHIFT0_STAGE0_SHIFT1_MASK) >> MTG_FILTER_STAGE_SHIFT0_STAGE0_SHIFT1_SHIFT)

/*
 * STAGE0_SHIFT0 (RW)
 *
 */
#define MTG_FILTER_STAGE_SHIFT0_STAGE0_SHIFT0_MASK (0xFU)
#define MTG_FILTER_STAGE_SHIFT0_STAGE0_SHIFT0_SHIFT (0U)
#define MTG_FILTER_STAGE_SHIFT0_STAGE0_SHIFT0_SET(x) (((uint32_t)(x) << MTG_FILTER_STAGE_SHIFT0_STAGE0_SHIFT0_SHIFT) & MTG_FILTER_STAGE_SHIFT0_STAGE0_SHIFT0_MASK)
#define MTG_FILTER_STAGE_SHIFT0_STAGE0_SHIFT0_GET(x) (((uint32_t)(x) & MTG_FILTER_STAGE_SHIFT0_STAGE0_SHIFT0_MASK) >> MTG_FILTER_STAGE_SHIFT0_STAGE0_SHIFT0_SHIFT)

/* Bitfield definition for register: FILTER_STAGE_SHIFT1 */
/*
 * STAGE5_SHIFT1 (RW)
 *
 */
#define MTG_FILTER_STAGE_SHIFT1_STAGE5_SHIFT1_MASK (0xF000U)
#define MTG_FILTER_STAGE_SHIFT1_STAGE5_SHIFT1_SHIFT (12U)
#define MTG_FILTER_STAGE_SHIFT1_STAGE5_SHIFT1_SET(x) (((uint32_t)(x) << MTG_FILTER_STAGE_SHIFT1_STAGE5_SHIFT1_SHIFT) & MTG_FILTER_STAGE_SHIFT1_STAGE5_SHIFT1_MASK)
#define MTG_FILTER_STAGE_SHIFT1_STAGE5_SHIFT1_GET(x) (((uint32_t)(x) & MTG_FILTER_STAGE_SHIFT1_STAGE5_SHIFT1_MASK) >> MTG_FILTER_STAGE_SHIFT1_STAGE5_SHIFT1_SHIFT)

/*
 * STAGE5_SHIFT0 (RW)
 *
 */
#define MTG_FILTER_STAGE_SHIFT1_STAGE5_SHIFT0_MASK (0xF00U)
#define MTG_FILTER_STAGE_SHIFT1_STAGE5_SHIFT0_SHIFT (8U)
#define MTG_FILTER_STAGE_SHIFT1_STAGE5_SHIFT0_SET(x) (((uint32_t)(x) << MTG_FILTER_STAGE_SHIFT1_STAGE5_SHIFT0_SHIFT) & MTG_FILTER_STAGE_SHIFT1_STAGE5_SHIFT0_MASK)
#define MTG_FILTER_STAGE_SHIFT1_STAGE5_SHIFT0_GET(x) (((uint32_t)(x) & MTG_FILTER_STAGE_SHIFT1_STAGE5_SHIFT0_MASK) >> MTG_FILTER_STAGE_SHIFT1_STAGE5_SHIFT0_SHIFT)

/*
 * STAGE4_SHIFT1 (RW)
 *
 */
#define MTG_FILTER_STAGE_SHIFT1_STAGE4_SHIFT1_MASK (0xF0U)
#define MTG_FILTER_STAGE_SHIFT1_STAGE4_SHIFT1_SHIFT (4U)
#define MTG_FILTER_STAGE_SHIFT1_STAGE4_SHIFT1_SET(x) (((uint32_t)(x) << MTG_FILTER_STAGE_SHIFT1_STAGE4_SHIFT1_SHIFT) & MTG_FILTER_STAGE_SHIFT1_STAGE4_SHIFT1_MASK)
#define MTG_FILTER_STAGE_SHIFT1_STAGE4_SHIFT1_GET(x) (((uint32_t)(x) & MTG_FILTER_STAGE_SHIFT1_STAGE4_SHIFT1_MASK) >> MTG_FILTER_STAGE_SHIFT1_STAGE4_SHIFT1_SHIFT)

/*
 * STAGE4_SHIFT0 (RW)
 *
 */
#define MTG_FILTER_STAGE_SHIFT1_STAGE4_SHIFT0_MASK (0xFU)
#define MTG_FILTER_STAGE_SHIFT1_STAGE4_SHIFT0_SHIFT (0U)
#define MTG_FILTER_STAGE_SHIFT1_STAGE4_SHIFT0_SET(x) (((uint32_t)(x) << MTG_FILTER_STAGE_SHIFT1_STAGE4_SHIFT0_SHIFT) & MTG_FILTER_STAGE_SHIFT1_STAGE4_SHIFT0_MASK)
#define MTG_FILTER_STAGE_SHIFT1_STAGE4_SHIFT0_GET(x) (((uint32_t)(x) & MTG_FILTER_STAGE_SHIFT1_STAGE4_SHIFT0_MASK) >> MTG_FILTER_STAGE_SHIFT1_STAGE4_SHIFT0_SHIFT)

/* Bitfield definition for register: FILTER_PARAM_SHIFT */
/*
 * ACC_SHIFT_PARAM (RW)
 *
 */
#define MTG_FILTER_PARAM_SHIFT_ACC_SHIFT_PARAM_MASK (0xF0000000UL)
#define MTG_FILTER_PARAM_SHIFT_ACC_SHIFT_PARAM_SHIFT (28U)
#define MTG_FILTER_PARAM_SHIFT_ACC_SHIFT_PARAM_SET(x) (((uint32_t)(x) << MTG_FILTER_PARAM_SHIFT_ACC_SHIFT_PARAM_SHIFT) & MTG_FILTER_PARAM_SHIFT_ACC_SHIFT_PARAM_MASK)
#define MTG_FILTER_PARAM_SHIFT_ACC_SHIFT_PARAM_GET(x) (((uint32_t)(x) & MTG_FILTER_PARAM_SHIFT_ACC_SHIFT_PARAM_MASK) >> MTG_FILTER_PARAM_SHIFT_ACC_SHIFT_PARAM_SHIFT)

/*
 * VEL_SHIFT_PARAM (RW)
 *
 */
#define MTG_FILTER_PARAM_SHIFT_VEL_SHIFT_PARAM_MASK (0xF000000UL)
#define MTG_FILTER_PARAM_SHIFT_VEL_SHIFT_PARAM_SHIFT (24U)
#define MTG_FILTER_PARAM_SHIFT_VEL_SHIFT_PARAM_SET(x) (((uint32_t)(x) << MTG_FILTER_PARAM_SHIFT_VEL_SHIFT_PARAM_SHIFT) & MTG_FILTER_PARAM_SHIFT_VEL_SHIFT_PARAM_MASK)
#define MTG_FILTER_PARAM_SHIFT_VEL_SHIFT_PARAM_GET(x) (((uint32_t)(x) & MTG_FILTER_PARAM_SHIFT_VEL_SHIFT_PARAM_MASK) >> MTG_FILTER_PARAM_SHIFT_VEL_SHIFT_PARAM_SHIFT)

/*
 * GAIN_K_SHIFT (RW)
 *
 */
#define MTG_FILTER_PARAM_SHIFT_GAIN_K_SHIFT_MASK (0xF00000UL)
#define MTG_FILTER_PARAM_SHIFT_GAIN_K_SHIFT_SHIFT (20U)
#define MTG_FILTER_PARAM_SHIFT_GAIN_K_SHIFT_SET(x) (((uint32_t)(x) << MTG_FILTER_PARAM_SHIFT_GAIN_K_SHIFT_SHIFT) & MTG_FILTER_PARAM_SHIFT_GAIN_K_SHIFT_MASK)
#define MTG_FILTER_PARAM_SHIFT_GAIN_K_SHIFT_GET(x) (((uint32_t)(x) & MTG_FILTER_PARAM_SHIFT_GAIN_K_SHIFT_MASK) >> MTG_FILTER_PARAM_SHIFT_GAIN_K_SHIFT_SHIFT)

/*
 * GAIN_T0_SHIFT (RW)
 *
 */
#define MTG_FILTER_PARAM_SHIFT_GAIN_T0_SHIFT_MASK (0xF0000UL)
#define MTG_FILTER_PARAM_SHIFT_GAIN_T0_SHIFT_SHIFT (16U)
#define MTG_FILTER_PARAM_SHIFT_GAIN_T0_SHIFT_SET(x) (((uint32_t)(x) << MTG_FILTER_PARAM_SHIFT_GAIN_T0_SHIFT_SHIFT) & MTG_FILTER_PARAM_SHIFT_GAIN_T0_SHIFT_MASK)
#define MTG_FILTER_PARAM_SHIFT_GAIN_T0_SHIFT_GET(x) (((uint32_t)(x) & MTG_FILTER_PARAM_SHIFT_GAIN_T0_SHIFT_MASK) >> MTG_FILTER_PARAM_SHIFT_GAIN_T0_SHIFT_SHIFT)

/*
 * GAIN_T1_SHIFT (RW)
 *
 */
#define MTG_FILTER_PARAM_SHIFT_GAIN_T1_SHIFT_MASK (0xF000U)
#define MTG_FILTER_PARAM_SHIFT_GAIN_T1_SHIFT_SHIFT (12U)
#define MTG_FILTER_PARAM_SHIFT_GAIN_T1_SHIFT_SET(x) (((uint32_t)(x) << MTG_FILTER_PARAM_SHIFT_GAIN_T1_SHIFT_SHIFT) & MTG_FILTER_PARAM_SHIFT_GAIN_T1_SHIFT_MASK)
#define MTG_FILTER_PARAM_SHIFT_GAIN_T1_SHIFT_GET(x) (((uint32_t)(x) & MTG_FILTER_PARAM_SHIFT_GAIN_T1_SHIFT_MASK) >> MTG_FILTER_PARAM_SHIFT_GAIN_T1_SHIFT_SHIFT)

/*
 * TP_SHIFT (RW)
 *
 */
#define MTG_FILTER_PARAM_SHIFT_TP_SHIFT_MASK (0xF00U)
#define MTG_FILTER_PARAM_SHIFT_TP_SHIFT_SHIFT (8U)
#define MTG_FILTER_PARAM_SHIFT_TP_SHIFT_SET(x) (((uint32_t)(x) << MTG_FILTER_PARAM_SHIFT_TP_SHIFT_SHIFT) & MTG_FILTER_PARAM_SHIFT_TP_SHIFT_MASK)
#define MTG_FILTER_PARAM_SHIFT_TP_SHIFT_GET(x) (((uint32_t)(x) & MTG_FILTER_PARAM_SHIFT_TP_SHIFT_MASK) >> MTG_FILTER_PARAM_SHIFT_TP_SHIFT_SHIFT)

/*
 * TZ_1_SHIFT (RW)
 *
 */
#define MTG_FILTER_PARAM_SHIFT_TZ_1_SHIFT_MASK (0xF0U)
#define MTG_FILTER_PARAM_SHIFT_TZ_1_SHIFT_SHIFT (4U)
#define MTG_FILTER_PARAM_SHIFT_TZ_1_SHIFT_SET(x) (((uint32_t)(x) << MTG_FILTER_PARAM_SHIFT_TZ_1_SHIFT_SHIFT) & MTG_FILTER_PARAM_SHIFT_TZ_1_SHIFT_MASK)
#define MTG_FILTER_PARAM_SHIFT_TZ_1_SHIFT_GET(x) (((uint32_t)(x) & MTG_FILTER_PARAM_SHIFT_TZ_1_SHIFT_MASK) >> MTG_FILTER_PARAM_SHIFT_TZ_1_SHIFT_SHIFT)

/*
 * TZ_SHIFT (RW)
 *
 */
#define MTG_FILTER_PARAM_SHIFT_TZ_SHIFT_MASK (0xFU)
#define MTG_FILTER_PARAM_SHIFT_TZ_SHIFT_SHIFT (0U)
#define MTG_FILTER_PARAM_SHIFT_TZ_SHIFT_SET(x) (((uint32_t)(x) << MTG_FILTER_PARAM_SHIFT_TZ_SHIFT_SHIFT) & MTG_FILTER_PARAM_SHIFT_TZ_SHIFT_MASK)
#define MTG_FILTER_PARAM_SHIFT_TZ_SHIFT_GET(x) (((uint32_t)(x) & MTG_FILTER_PARAM_SHIFT_TZ_SHIFT_MASK) >> MTG_FILTER_PARAM_SHIFT_TZ_SHIFT_SHIFT)

/* Bitfield definition for register: FILTER_TIME_SHIFT */
/*
 * ACC_SHIFT_TIME1 (RW)
 *
 */
#define MTG_FILTER_TIME_SHIFT_ACC_SHIFT_TIME1_MASK (0xF000U)
#define MTG_FILTER_TIME_SHIFT_ACC_SHIFT_TIME1_SHIFT (12U)
#define MTG_FILTER_TIME_SHIFT_ACC_SHIFT_TIME1_SET(x) (((uint32_t)(x) << MTG_FILTER_TIME_SHIFT_ACC_SHIFT_TIME1_SHIFT) & MTG_FILTER_TIME_SHIFT_ACC_SHIFT_TIME1_MASK)
#define MTG_FILTER_TIME_SHIFT_ACC_SHIFT_TIME1_GET(x) (((uint32_t)(x) & MTG_FILTER_TIME_SHIFT_ACC_SHIFT_TIME1_MASK) >> MTG_FILTER_TIME_SHIFT_ACC_SHIFT_TIME1_SHIFT)

/*
 * VEL_SHIFT_TIME1 (RW)
 *
 */
#define MTG_FILTER_TIME_SHIFT_VEL_SHIFT_TIME1_MASK (0xF00U)
#define MTG_FILTER_TIME_SHIFT_VEL_SHIFT_TIME1_SHIFT (8U)
#define MTG_FILTER_TIME_SHIFT_VEL_SHIFT_TIME1_SET(x) (((uint32_t)(x) << MTG_FILTER_TIME_SHIFT_VEL_SHIFT_TIME1_SHIFT) & MTG_FILTER_TIME_SHIFT_VEL_SHIFT_TIME1_MASK)
#define MTG_FILTER_TIME_SHIFT_VEL_SHIFT_TIME1_GET(x) (((uint32_t)(x) & MTG_FILTER_TIME_SHIFT_VEL_SHIFT_TIME1_MASK) >> MTG_FILTER_TIME_SHIFT_VEL_SHIFT_TIME1_SHIFT)

/*
 * ACC_SHIFT_TIME0 (RW)
 *
 */
#define MTG_FILTER_TIME_SHIFT_ACC_SHIFT_TIME0_MASK (0xF0U)
#define MTG_FILTER_TIME_SHIFT_ACC_SHIFT_TIME0_SHIFT (4U)
#define MTG_FILTER_TIME_SHIFT_ACC_SHIFT_TIME0_SET(x) (((uint32_t)(x) << MTG_FILTER_TIME_SHIFT_ACC_SHIFT_TIME0_SHIFT) & MTG_FILTER_TIME_SHIFT_ACC_SHIFT_TIME0_MASK)
#define MTG_FILTER_TIME_SHIFT_ACC_SHIFT_TIME0_GET(x) (((uint32_t)(x) & MTG_FILTER_TIME_SHIFT_ACC_SHIFT_TIME0_MASK) >> MTG_FILTER_TIME_SHIFT_ACC_SHIFT_TIME0_SHIFT)

/*
 * VEL_SHIFT_TIME0 (RW)
 *
 */
#define MTG_FILTER_TIME_SHIFT_VEL_SHIFT_TIME0_MASK (0xFU)
#define MTG_FILTER_TIME_SHIFT_VEL_SHIFT_TIME0_SHIFT (0U)
#define MTG_FILTER_TIME_SHIFT_VEL_SHIFT_TIME0_SET(x) (((uint32_t)(x) << MTG_FILTER_TIME_SHIFT_VEL_SHIFT_TIME0_SHIFT) & MTG_FILTER_TIME_SHIFT_VEL_SHIFT_TIME0_MASK)
#define MTG_FILTER_TIME_SHIFT_VEL_SHIFT_TIME0_GET(x) (((uint32_t)(x) & MTG_FILTER_TIME_SHIFT_VEL_SHIFT_TIME0_MASK) >> MTG_FILTER_TIME_SHIFT_VEL_SHIFT_TIME0_SHIFT)

/* Bitfield definition for register: FILTER_FF_SHIFT */
/*
 * OUTPUT_ACC_SHIFT (RW)
 *
 */
#define MTG_FILTER_FF_SHIFT_OUTPUT_ACC_SHIFT_MASK (0xF000U)
#define MTG_FILTER_FF_SHIFT_OUTPUT_ACC_SHIFT_SHIFT (12U)
#define MTG_FILTER_FF_SHIFT_OUTPUT_ACC_SHIFT_SET(x) (((uint32_t)(x) << MTG_FILTER_FF_SHIFT_OUTPUT_ACC_SHIFT_SHIFT) & MTG_FILTER_FF_SHIFT_OUTPUT_ACC_SHIFT_MASK)
#define MTG_FILTER_FF_SHIFT_OUTPUT_ACC_SHIFT_GET(x) (((uint32_t)(x) & MTG_FILTER_FF_SHIFT_OUTPUT_ACC_SHIFT_MASK) >> MTG_FILTER_FF_SHIFT_OUTPUT_ACC_SHIFT_SHIFT)

/*
 * FILTER_ACC_SHIFT (RW)
 *
 */
#define MTG_FILTER_FF_SHIFT_FILTER_ACC_SHIFT_MASK (0xF00U)
#define MTG_FILTER_FF_SHIFT_FILTER_ACC_SHIFT_SHIFT (8U)
#define MTG_FILTER_FF_SHIFT_FILTER_ACC_SHIFT_SET(x) (((uint32_t)(x) << MTG_FILTER_FF_SHIFT_FILTER_ACC_SHIFT_SHIFT) & MTG_FILTER_FF_SHIFT_FILTER_ACC_SHIFT_MASK)
#define MTG_FILTER_FF_SHIFT_FILTER_ACC_SHIFT_GET(x) (((uint32_t)(x) & MTG_FILTER_FF_SHIFT_FILTER_ACC_SHIFT_MASK) >> MTG_FILTER_FF_SHIFT_FILTER_ACC_SHIFT_SHIFT)

/*
 * OUTPUT_VEL_SHIFT (RW)
 *
 */
#define MTG_FILTER_FF_SHIFT_OUTPUT_VEL_SHIFT_MASK (0xF0U)
#define MTG_FILTER_FF_SHIFT_OUTPUT_VEL_SHIFT_SHIFT (4U)
#define MTG_FILTER_FF_SHIFT_OUTPUT_VEL_SHIFT_SET(x) (((uint32_t)(x) << MTG_FILTER_FF_SHIFT_OUTPUT_VEL_SHIFT_SHIFT) & MTG_FILTER_FF_SHIFT_OUTPUT_VEL_SHIFT_MASK)
#define MTG_FILTER_FF_SHIFT_OUTPUT_VEL_SHIFT_GET(x) (((uint32_t)(x) & MTG_FILTER_FF_SHIFT_OUTPUT_VEL_SHIFT_MASK) >> MTG_FILTER_FF_SHIFT_OUTPUT_VEL_SHIFT_SHIFT)

/*
 * FILTER_VEL_SHIFT (RW)
 *
 */
#define MTG_FILTER_FF_SHIFT_FILTER_VEL_SHIFT_MASK (0xFU)
#define MTG_FILTER_FF_SHIFT_FILTER_VEL_SHIFT_SHIFT (0U)
#define MTG_FILTER_FF_SHIFT_FILTER_VEL_SHIFT_SET(x) (((uint32_t)(x) << MTG_FILTER_FF_SHIFT_FILTER_VEL_SHIFT_SHIFT) & MTG_FILTER_FF_SHIFT_FILTER_VEL_SHIFT_MASK)
#define MTG_FILTER_FF_SHIFT_FILTER_VEL_SHIFT_GET(x) (((uint32_t)(x) & MTG_FILTER_FF_SHIFT_FILTER_VEL_SHIFT_MASK) >> MTG_FILTER_FF_SHIFT_FILTER_VEL_SHIFT_SHIFT)

/* Bitfield definition for register: FILTER_TIME1_SW_ADJUST */
/*
 * TIME (RW)
 *
 */
#define MTG_FILTER_TIME1_SW_ADJUST_TIME_MASK (0xFFFFFFFFUL)
#define MTG_FILTER_TIME1_SW_ADJUST_TIME_SHIFT (0U)
#define MTG_FILTER_TIME1_SW_ADJUST_TIME_SET(x) (((uint32_t)(x) << MTG_FILTER_TIME1_SW_ADJUST_TIME_SHIFT) & MTG_FILTER_TIME1_SW_ADJUST_TIME_MASK)
#define MTG_FILTER_TIME1_SW_ADJUST_TIME_GET(x) (((uint32_t)(x) & MTG_FILTER_TIME1_SW_ADJUST_TIME_MASK) >> MTG_FILTER_TIME1_SW_ADJUST_TIME_SHIFT)

/* Bitfield definition for register: FILTER_TIME0_SW_ADJUST */
/*
 * TIME (RW)
 *
 */
#define MTG_FILTER_TIME0_SW_ADJUST_TIME_MASK (0xFFFFFFFFUL)
#define MTG_FILTER_TIME0_SW_ADJUST_TIME_SHIFT (0U)
#define MTG_FILTER_TIME0_SW_ADJUST_TIME_SET(x) (((uint32_t)(x) << MTG_FILTER_TIME0_SW_ADJUST_TIME_SHIFT) & MTG_FILTER_TIME0_SW_ADJUST_TIME_MASK)
#define MTG_FILTER_TIME0_SW_ADJUST_TIME_GET(x) (((uint32_t)(x) & MTG_FILTER_TIME0_SW_ADJUST_TIME_MASK) >> MTG_FILTER_TIME0_SW_ADJUST_TIME_SHIFT)

/* Bitfield definition for register: FILTER_ERROR_LIMIT_L */
/*
 * ERROR_LIMIT_L (RW)
 *
 */
#define MTG_FILTER_ERROR_LIMIT_L_ERROR_LIMIT_L_MASK (0xFFFFFFFFUL)
#define MTG_FILTER_ERROR_LIMIT_L_ERROR_LIMIT_L_SHIFT (0U)
#define MTG_FILTER_ERROR_LIMIT_L_ERROR_LIMIT_L_SET(x) (((uint32_t)(x) << MTG_FILTER_ERROR_LIMIT_L_ERROR_LIMIT_L_SHIFT) & MTG_FILTER_ERROR_LIMIT_L_ERROR_LIMIT_L_MASK)
#define MTG_FILTER_ERROR_LIMIT_L_ERROR_LIMIT_L_GET(x) (((uint32_t)(x) & MTG_FILTER_ERROR_LIMIT_L_ERROR_LIMIT_L_MASK) >> MTG_FILTER_ERROR_LIMIT_L_ERROR_LIMIT_L_SHIFT)

/* Bitfield definition for register: FILTER_ERROR_LIMIT_H */
/*
 * ERROR_LIMIT_H (RW)
 *
 */
#define MTG_FILTER_ERROR_LIMIT_H_ERROR_LIMIT_H_MASK (0xFFFFFFFFUL)
#define MTG_FILTER_ERROR_LIMIT_H_ERROR_LIMIT_H_SHIFT (0U)
#define MTG_FILTER_ERROR_LIMIT_H_ERROR_LIMIT_H_SET(x) (((uint32_t)(x) << MTG_FILTER_ERROR_LIMIT_H_ERROR_LIMIT_H_SHIFT) & MTG_FILTER_ERROR_LIMIT_H_ERROR_LIMIT_H_MASK)
#define MTG_FILTER_ERROR_LIMIT_H_ERROR_LIMIT_H_GET(x) (((uint32_t)(x) & MTG_FILTER_ERROR_LIMIT_H_ERROR_LIMIT_H_MASK) >> MTG_FILTER_ERROR_LIMIT_H_ERROR_LIMIT_H_SHIFT)

/* Bitfield definition for register: FILTER_TIMEOUT_CNT */
/*
 * TIMEOUT_CNT (RW)
 *
 */
#define MTG_FILTER_TIMEOUT_CNT_TIMEOUT_CNT_MASK (0xFFFFFFFFUL)
#define MTG_FILTER_TIMEOUT_CNT_TIMEOUT_CNT_SHIFT (0U)
#define MTG_FILTER_TIMEOUT_CNT_TIMEOUT_CNT_SET(x) (((uint32_t)(x) << MTG_FILTER_TIMEOUT_CNT_TIMEOUT_CNT_SHIFT) & MTG_FILTER_TIMEOUT_CNT_TIMEOUT_CNT_MASK)
#define MTG_FILTER_TIMEOUT_CNT_TIMEOUT_CNT_GET(x) (((uint32_t)(x) & MTG_FILTER_TIMEOUT_CNT_TIMEOUT_CNT_MASK) >> MTG_FILTER_TIMEOUT_CNT_TIMEOUT_CNT_SHIFT)

/* Bitfield definition for register: FILTER_REV_LOCK */
/*
 * REV_STATUS (RO)
 *
 */
#define MTG_FILTER_REV_LOCK_REV_STATUS_MASK (0xFFFFFFFFUL)
#define MTG_FILTER_REV_LOCK_REV_STATUS_SHIFT (0U)
#define MTG_FILTER_REV_LOCK_REV_STATUS_GET(x) (((uint32_t)(x) & MTG_FILTER_REV_LOCK_REV_STATUS_MASK) >> MTG_FILTER_REV_LOCK_REV_STATUS_SHIFT)

/* Bitfield definition for register: FILTER_POS_LOCK */
/*
 * POS_STATUS (RO)
 *
 */
#define MTG_FILTER_POS_LOCK_POS_STATUS_MASK (0xFFFFFFFFUL)
#define MTG_FILTER_POS_LOCK_POS_STATUS_SHIFT (0U)
#define MTG_FILTER_POS_LOCK_POS_STATUS_GET(x) (((uint32_t)(x) & MTG_FILTER_POS_LOCK_POS_STATUS_MASK) >> MTG_FILTER_POS_LOCK_POS_STATUS_SHIFT)

/* Bitfield definition for register: FILTER_VEL_LOCK */
/*
 * VEL_STATUS (RO)
 *
 */
#define MTG_FILTER_VEL_LOCK_VEL_STATUS_MASK (0xFFFFFFFFUL)
#define MTG_FILTER_VEL_LOCK_VEL_STATUS_SHIFT (0U)
#define MTG_FILTER_VEL_LOCK_VEL_STATUS_GET(x) (((uint32_t)(x) & MTG_FILTER_VEL_LOCK_VEL_STATUS_MASK) >> MTG_FILTER_VEL_LOCK_VEL_STATUS_SHIFT)

/* Bitfield definition for register: FILTER_ACC_LOCK */
/*
 * ACC_STATUS (RO)
 *
 */
#define MTG_FILTER_ACC_LOCK_ACC_STATUS_MASK (0xFFFFFFFFUL)
#define MTG_FILTER_ACC_LOCK_ACC_STATUS_SHIFT (0U)
#define MTG_FILTER_ACC_LOCK_ACC_STATUS_GET(x) (((uint32_t)(x) & MTG_FILTER_ACC_LOCK_ACC_STATUS_MASK) >> MTG_FILTER_ACC_LOCK_ACC_STATUS_SHIFT)



/* CMD register group index macro definition */
#define MTG_CMD_0 (0UL)
#define MTG_CMD_1 (1UL)
#define MTG_CMD_2 (2UL)
#define MTG_CMD_3 (3UL)

/* TRA register group index macro definition */
#define MTG_TRA_0 (0UL)
#define MTG_TRA_1 (1UL)

/* EVENT register group index macro definition */
#define MTG_EVENT_0 (0UL)
#define MTG_EVENT_1 (1UL)
#define MTG_EVENT_2 (2UL)
#define MTG_EVENT_3 (3UL)


#endif /* HPM_MTG_H */
